赛灵思7系列FPGA存储器接口用户指南

FPGA

需积分: 49 45 浏览量更新于2024-07-09 收藏 15.3MB PDF 举报

身份认证购VIP最低享 7 折!

30元优惠券

"赛灵思7系列FPGA存储器接口解决方案用户指南，版本1.7，发布日期2012年10月16日。该文档提供了详细信息，帮助用户理解和利用7系列FPGA进行内存接口设计。" 在赛灵思的7系列FPGA中，内存接口解决方案是关键组成部分，它允许FPGA高效地与各种类型的内存设备通信，如DDR、DDR2、DDR3等。这份用户指南涵盖了以下几个核心知识点： 1. **内存接口架构**：7系列FPGA的内存接口设计采用了先进的架构，包括高性能的硬核内存控制器（MIG - Memory Interface Generator）和灵活的内存接口IP，能够支持不同内存标准的时序要求和数据速率。 2. **MIG介绍**：MIG是一个自动生成工具，可根据特定内存类型和速度等级配置生成内存控制器。它包含预优化的时序收敛逻辑，可以简化内存接口设计，同时确保满足严格的内存时序约束。 3. **内存类型支持**：7系列FPGA支持多种内存类型，包括DDR3 SDRAM、DDR2 SDRAM、LPDDR2 SDRAM以及同步静态RAM（SRAM）。每个内存类型都有其独特的性能特性和功耗需求，MIG可以根据这些特性进行定制化配置。 4. **接口配置**：用户可以通过配置文件定义内存接口的具体参数，如总线宽度、bank数量、内存时钟频率等。这些参数的设定直接影响到系统的带宽和功耗。 5. **时序分析**：用户指南详细介绍了如何进行时序分析，以确保设计符合内存设备的时序要求。这包括读写命令的延迟、数据有效时间、预充电周期等关键时序参数。 6. **错误检测与纠正**：7系列FPGA的内存接口还包含了错误检测和纠正功能，如ECC（Error Correction Code），增强了系统可靠性。 7. **电源管理**：为了降低功耗，7系列FPGA的内存接口支持动态电压和频率调整（DVFS）以及低功耗模式，如深度睡眠模式。 8. **设计流程**：用户指南会详细阐述从设置项目、配置MIG、综合、实现、时序分析到硬件调试的完整设计流程，帮助用户顺利进行内存接口设计。 9. **兼容性与互操作性**：7系列FPGA内存接口方案考虑了与其他系统组件的兼容性，包括处理器、接口桥接芯片等，确保在整个系统中无缝集成。 10. **示例设计和验证**：文档提供了一系列示例设计，包括基础配置和高级特性应用，帮助开发者快速上手并验证设计方案。通过这份用户指南，设计者可以获得详尽的指导，以充分利用赛灵思7系列FPGA的内存接口能力，创建高效、可靠的内存系统。同时，需要注意的是，文档中的所有信息都是“按原样”提供的，赛灵思不提供任何明示或暗示的保修，使用者应自行承担使用风险。

资源详情

资源推荐

16 www.xilinx.com 7 Series FPGAs Memory Interface Solutions

UG586 October 16, 2012

Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution

MIG Output Options

1. Select the Create Design radio button to create a new memory controller design. Enter

a component name in the Component Name field (Figure 1-8).

2. Choose the number of controllers to be generated. This option determines the

replication of further pages.

3. DDR2 and DDR3 SDRAM designs support the memory-mapped AXI4 interface. The

AXI4 interface is implemented in Verilog only. If an AXI4 interface is required, select

the language as “Verilog” in the CORE Generator tool before invoking the MIG tool. If

the AXI4 interface is not selected, the user interface (UI) is the primary interface. The

axi_7series_ddrx IP from the EDK flow only supports DDR3 SDRAMs and has the AXI

support always turned on.

MIG outputs are generated with the folder name <component name>.

Note:

Only alphanumeric characters can be used for <component name>. Special characters

cannot be used. This name should always start with an alphabetical character and can end with

an alphanumeric character.

When invoked from XPS, the component name is corrected to be the IP instance name

from XPS.

4. Click Next to display the Pin Compatible FPGAs page.

X-Ref Target - Figure 1-8

Figure 1-8: MIG Output Options

UG586_c1_09_120311

20 www.xilinx.com 7 Series FPGAs Memory Interface Solutions

UG586 October 16, 2012

Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution

If the design has multiple controllers, the controller options page is repeated for each of the

controllers. This page is partitioned into a maximum of nine sections. The number of

partitions depends on the type of memory selected. The controller options page also

contains these pull-down menus to modify different features of the design:

• Frequency – This feature indicates the operating frequency for all the controllers. The

frequency block is limited by factors such as the selected FPGA and device speed

grade. In the EDK flow, an extra check box (selected by default) allows the user to

specify that the frequency information should be calculated automatically from EDK.

• Input Clock Period – The desired input clock period is selected from the list. These

values are determined by the memory clock period chosen and the allowable limits of

the parameters. See Design Guidelines, page 144 for more information on the PLL

parameter limits.

• PHY to Controller Clock Ratio – This feature determines the ratio of the physical

layer (memory) clock frequency to the controller and user interface clock frequency.

The 2:1 ratio lowers the maximum memory interface frequency due to fabric timing

limitations. The user interface data bus width of the 2:1 ratio is 4 times the width of

the physical memory interface width, while the bus width of the 4:1 ratio is 8 times the

physical memory interface width. The 2:1 ratio has lower latency. The 4:1 ratio is

necessary for the highest data rates.

• Vccaux_io – Vccaux_io is set based on the period/frequency setting. 2.0V is required

at the highest frequency settings in the High Performance column. The MIG tool

automatically selects 2.0V when required. Either 1.8 or 2.0V can be used at lower

frequencies. Groups of banks share the Vccaux_io supply. See the 7 Series FPGAs

SelectIO Resources User Guide [Ref 1] and the 7 Series FPGAs Packaging and Pinout

Specification [Ref 2] for more information.

• Memory Type – This feature selects the type of memory parts used in the design.

• Memory Part – This option selects a memory part for the design. Selections can be

made from the list or a new part can be created.

• Data Width – The data width value can be selected here based on the memory type

selected earlier. The list shows all supported data widths for the selected part. One of

the data widths can be selected. These values are generally multiples of the individual

device data widths. In some cases, the width might not be an exact multiple. For

example, 16 bits is the default data width for x16 components, but 8 bits is also a valid

value.

• Data Mask – This option allocates data mask pins when selected. This option should

be deselected to deallocate data mask pins and increase pin efficiency. This option is

disabled for memory parts that do not support data mask.

• Ordering – This feature allows the memory controller to reorder commands to

improve the memory bus efficiency.

• Memory Details – The bottom of the Controller Options page (Figure 1-11, page 19)

displays the details for the selected memory configuration (Figure 1-12).

1. Select the appropriate frequency. Either use the spin box or enter a valid value using

the keyboard. Values entered are restricted based on the minimum and maximum

frequencies supported.

X-Ref Target - Figure 1-12

Figure 1-12: Memory Details

UG586_c1_20_091410

剩余357页未读，继续阅读

通信fpga小白白

粉丝: 0
资源: 4

赛灵思7系列FPGA存储器接口用户指南

UG586赛灵思 DDR3的IP核（MIG）详细文档

ug586_7Series FPGAs Memory Interface Solutions v1.7.pdf

FPGA基础入门－DDR2读写工程文件

ug586_7series_mis

ug471_7series_selectio.pdf

ug476_7series_transceivers.pdf

ug586_7series_mispdf文档下载

ug470_7series_config中文

怎么测试ug480_7series_xadc

获取https://www.wandoujia.com/apps/8130841/strategy?spm=aligames_platform_ug.wdj_seo.0.0.37965db8I6C3zN下所有链接地址并以表格保存在本地

ug_nios2_flash_programmer.pdf

if ( (TP_State.X > 0) && (TP_State.X < 239 ) ) { if ( (TP_State.Y > 0) && (TP_State.Y < 319 ) ) { /*====LED-ON=======*/ GPIO_SetBits(GPIOD , GPIO_Pin_8); UG_TouchUpdate(TP_State.X,TP_State.Y,TOUCH_STATE_PRESSED); //触摸坐标更新 } }

A USER ERROR has occurred: Couldn't read file. Error was: ../02.mapping/L353.sort.markdup.bam with exception: Cannot read non-existent file: file:///home/ug1341/Part1.variant_calling/03.SNP_indel_bcftools/../02.mapping/L353.sort.markdup.bam 怎么解决

uvm_ralgen_ug.pdf

UG_WINDOW window_2; UG_OBJECT obj_buff_wnd_2[MAX_OBJECTS]; UG_BUTTON button2_1; UG_TEXTBOX textbox2_1; UG_TEXTBOX textbox2_2; UG_IMAGE image2_1;

UG_WINDOW window_1; UG_OBJECT obj_buff_wnd_1[MAX_OBJECTS]; UG_BUTTON button1_1; UG_BUTTON button1_2; UG_BUTTON button1_3; UG_BUTTON button1_4; UG_BUTTON button1_5; UG_BUTTON button1_6;

最新资源

if ( (TP_State.X > 0) && (TP_State.X < 239 ) ) { if ( (TP_State.Y > 0) && (TP_State.Y < 319 ) ) { /====LED-ON=======/ GPIO_SetBits(GPIOD , GPIO_Pin_8); UG_TouchUpdate(TP_State.X,TP_State.Y,TOUCH_STATE_PRESSED); //触摸坐标更新 } }