Xilinx Video Into AXI4-Stream 设计与实现教程

video

AXI4-Stream

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"Video In to AXI4-Stream 是Xilinx公司提供的一个LogiCORE IP，主要用于处理视频数据流的输入，并将其转化为AXI4-Stream接口格式。该IP产品适用于各种视频处理应用，如图像处理、视频分析等。本教程涵盖了从概述、产品规格、设计指导到设计流程步骤、详细示例设计、测试平台以及迁移和升级策略等多个方面，旨在帮助用户理解和有效利用这一IP核进行系统设计。章节1：概述这一章介绍了Video In to AXI4-Stream IP的主要特性，包括其在视频处理应用中的作用和适用场景。同时，它还提供了关于授权和订购信息的详细说明。章节2：产品规格此部分详细阐述了该IP遵循的视频标准，性能指标，以及在硬件资源上的占用情况，包括接口类型和功能。资源利用率章节通常会列出逻辑单元（LUTs）、触发器（FFs）以及其他关键资源的估计使用量。章节3：设计指导本章为用户提供了一般性的设计准则，讨论了在系统设计中需要考虑的因素，如时序模式、隔行扫描操作等。此外，还对核心模块的功能进行了描述，帮助用户理解IP如何工作。章节4：设计流程步骤这一章详细介绍了如何定制和生成这个IP，包括必要的约束设置、仿真、综合以及实现等设计阶段。用户可以参考这些步骤来集成IP到他们的设计中。章节5：详细示例设计本章提供了一个实际的设计示例，通过具体的案例展示IP的使用方法，帮助用户更直观地学习如何运用Video In to AXI4-Stream。章节6：测试平台这里介绍了一个演示测试平台，用于验证IP的功能正确性。这通常包括仿真验证和硬件测试，确保IP与其他系统组件的兼容性。附录A：验证、合规性和互操作性这部分详述了IP的仿真验证过程，硬件测试步骤以及与其他系统的互操作性验证，确保IP在实际应用中的可靠性。附录B：迁移和升级对于那些从旧版工具或IP版本迁移至Vivado Design Suite的用户，这一章提供了详细的迁移和升级指南。附录C：调试最后，附录C介绍了IP的调试方法，帮助用户解决在设计和实现过程中可能遇到的问题。通过这个IP产品指南，开发者将能够深入理解Video In to AXI4-Stream的工作原理，有效地将其整合到基于Xilinx FPGA或SoC的视频处理系统中，实现高效的数据传输和处理。"

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Video In to AXI4-Stream www.xilinx.com 8

PG043 October 4, 2017

Chapter 2

Product Specification

Standards

The Video In to AXI4-Stream core is compliant with the AXI4-Stream Video Protocol. Refer

to the Video IP: AXI Feature Adoption section of the Vivado AXI Reference Guide (UG1037)

[Ref 5] for additional information.

Performance

The following sections detail the performance characteristics of the Video In to

AXI4-Stream core.

Maximum Frequencies

This section contains typical clock frequencies for the target devices. The maximum

achievable clock frequency can vary. The maximum achievable clock frequency and all

resource counts can be affected by other tool options, additional logic in the FPGA device,

using a different version of Xilinx tools and other factors.

Latency

When the downstream processing block on the AXI4-Stream bus can take data at the pixel

rate or faster, the typical latency through the Video In to AXI4-Stream core is 6 cycles of

vid_io_in_clk + 3 cycles of aclk .

If the downstream block takes pixels at a slower rate, the FIFO is used to balance the

mismatch in the input and output rates over the course of lines and frames. This storage of

pixels in the FIFO adds to the latency and varies according to the data flow in and out of the

core.

Throughput

The average data rates of active pixels on the AXI4-Stream interface matches the average

rate of active pixels in on the Video bus. However, the clock rates of the input and output

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Video In to AXI4-Stream www.xilinx.com 9

PG043 October 4, 2017

Chapter 2: Product Specification

need not match. Because the AXI4-Stream bus does not carry blank pixels, the clock rate

can be lower than the video clock rate and still have sufficient bandwidth to meet the

average rate requirement. Additional FIFO depth is required to smooth the mismatch in

instantaneous rates. Both the input video pixel clock (Fvclk) and the rate of the

AXI4-Stream Clock (Faclk) are limited by the overall Fmax.

If Faclk is equal to or greater than Fvclk, only the minimum buffer size (32 locations) is

required. This assumes that the cores connected downstream of the Video In to

AXI4-Stream core can sink data at the full video rate. For example, the downstream core can

accept data in a virtually continuous stream with gaps occurring only following EOL, and

each line consecutively with line gaps only preceding SOF. In this scenario, the FIFO empties

after the EOL on each line.

If Faclk is less than Fvclk, additional buffering is required. The FIFO must be large

enough to handle the differential in the rate that pixels are coming in on the video clock,

and the slower rate that they can go out on the AXI4-Stream bus using aclk. For aclk

frequencies above the line average but below that of vclk, the input FIFO depth must be:

FIFO depth min =32 + Active Pixels * Fvclk/Faclk

If the downstream processing core accepts data at a lower rate than the aclk, additional

buffering is required in an amount sufficient to prevent the FIFO from overflowing during

frame transmission.

Resource Utilization

For details about resource utilization, visit Performance and Resource Utilization.

Core Interfaces

Port Descriptions

The Video In to AXI4-Stream core uses industry-standard control and data interfaces to

connect to other system components. The following sections describe the various interfaces

available with the core. Figure 2-1 illustrates an I/O diagram of the Video In to AXI4-Stream

core. Not all of the timing signals are required by this core, however it also passes these

signals to a Xilinx Video Timing Controller which, depending on its configuration, may

require certain signals. Therefore all timing signals are present. For the Video In to AXI4

Stream core, the data valid is always required. Also, either a vertical sync or a vertical blank

input is required.

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