2015 Altera Quartus II Verilog Simulation Handbook (Volume 3: Verification)

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"《Quartus II Handbook Volume 3 - 2015》是Altera公司针对其FPGA产品的官方手册，专注于2015年的Verilog HDL设计验证部分。该手册强调了在实际编程设备之前通过模拟验证设计行为的重要性。Quartus II软件提供了对RTL级和门级设计的模拟支持，在多个主流EDA（电子设计自动化）工具中运行，包括Aldec的Active-HDL、Riviera-PRO，Cadence的Incisive Enterprise，Mentor Graphics的ModelSim-Altera、ModelSim PE、ModelSim SE以及Synopsys的QuestaSim。首先，设计者需要设置一个适合的模拟工作环境，这包括选择并安装相应的EDA模拟器，如Table 1-1所示，不同的厂商提供不同的模拟器版本，如Aldec的Active-HDL适用于Windows平台，而Cadence和Mentor Graphics的产品则支持Windows和Linux系统。这些模拟器版本对应着不同的功能和兼容性，用户应根据自己的项目需求和开发环境选择最合适的工具。在模拟阶段，Quartus II允许编译和整合设计模型库，这涉及到将设计文件转换成仿真器能够理解的形式。用户需编写或导入RTL级或门级描述语言（Verilog或 VHDL）的代码，并将其与Quartus II集成，以便进行逻辑验证和时序分析。在模拟过程中，可以检查设计的逻辑行为是否符合预期，包括电路功能、信号完整性、电源管理等方面，这对于发现早期设计错误和性能优化至关重要。此外，手册还可能涵盖如何配置仿真设置，如时钟频率、电源模式、噪声分析等，以及如何解读和分析模拟结果。它可能还会讨论高级功能，如虚拟原型验证（Vivado IP Integrator）、仿真信号探查工具等，这些都是确保设计质量的关键步骤。《Quartus II Handbook Volume 3 - 2015》为 Altera FPGA的设计者提供了详尽的指南，从基础到高级技巧，帮助他们在设计流程中有效地利用模拟来验证和优化他们的硬件设计，从而提高产品质量和生产效率。"

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Before you begin

By default, the x_on_violation_option logic option is enabled for all design registers, resulting in an

output of “X” at timing violation. To disable “X” propagation at timing violations on a specific register,

disable the x_on_violation_option logic option for the specific register, as shown in the following

example from the Quartus II Settings File (.qsf).

set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to \ <register_name>

Passing Parameter Information from Verilog HDL to VHDL

You must use in-line parameters to pass values from Verilog HDL to VHDL.

Before you begin

By default, the x_on_violation_option logic option is enabled for all design registers, resulting in an

output of “X” at timing violation. To disable “X” propagation at timing violations on a specific register,

disable the x_on_violation_option logic option for the specific register, as shown in the following

example from the Quartus II Settings File (.qsf).

set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to \ <register_name>

Example 2-1: In-line Parameter Passing Example

lpm_add_sub#(.lpm_width(12), .lpm_direction("Add"),

.lpm_type("LPM_ADD_SUB"),

.lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO" ))

lpm_add_sub_component (

.dataa (dataa),

.datab (datab),

.result (sub_wire0)

);

Note:

The sequence of the parameters depends on the sequence of the GENERIC in the

VHDL component declaration.

Increasing Simulation Speed

By default, the ModelSim and QuestaSim software runs in a debug-optimized mode.

Before you begin

To run the ModelSim and QuestaSim software in speed-optimized mode, add the following two vlog

command-line switches. In this mode, module boundaries are flattened and loops are optimized, which

eliminates levels of debugging hierarchy and may result in faster simulation. This switch is not supported

in the ModelSim-Altera simulator.

vlog -fast -05

Simulating Transport Delays

By default, the ModelSim and QuestaSim software filter out all pulses that are shorter than the

propagation delay between primitives.

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Passing Parameter Information from Verilog HDL to VHDL

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Turning on the transport delay options in the ModelSim and QuestaSim software prevents the simulator

from filtering out these pulses.

Table 2-1: Transport Delay Simulation Options (ModelSim and QuestaSim)

Option Description

+transport_path_delays Use when simulation pulses are shorter than the

delay in a gate-level primitive. You must include the

+pulse_e/number and +pulse_r/number options.

+transport_int_delays Use when simulation pulses are shorter than the

interconnect delay between gate-level primitives.

You must include the +pulse_int_e/number and

+pulse_int_r/number options.

Note: The +transport_path_delays and +transport_path_delays options apply automatically during

NativeLink gate-level timing simulation. For more information about either of these options, refer

to the ModelSim-Altera Command Reference installed with the ModelSim and QuestaSim

software.

The following ModelSim and QuestaSim software command shows the command line syntax to perform

a gate-level timing simulation with the device family library:

vsim -t 1ps -L stratixii -sdftyp /i1=filtref_vhd.sdo work.filtref_vhd_vec_tst \

+transport_int_delays +transport_path_delays

Viewing Error Messages

ModelSim and QuestaSim error and warning messages are tagged with a vsim or vcom code. To

determine the cause and resolution for a vsim or vcom error or warning, use the verror command.

For example, ModelSim may return the following error:

# ** Error: C:/altera_trn/DUALPORT_TRY/simulation/modelsim/DUALPORT_TRY.vho(31):

(vcom-1136) Unknown identifier "stratixiv"

In this case, type the following command:

verror 1136

The following description appears:

# vcom Message # 1136:

# The specified name was referenced but was not found. This indicates

# that either the name specified does not exist or is not visible at

# this point in the code.

Generating Power Analysis Files

To generate a timing Value Change Dump File (.vcd) for power analysis, you must first generate a

<filename>_dump_all_vcd_nodes.tcl script file in the Quartus II software. You can then run the script from

the ModelSim, QuestaSim, or ModelSim-Altera software to generate a timing <filename>.vcd. for use in

the Quartus II PowerPlay power analyzer.

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Viewing Error Messages

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Before you begin

To generate and use a .vcd for power analysis, follow these steps:

1. In the Quartus II software, click Assignments > Settings.

2. Under EDA Tool Settings, click Simulation.

3. Turn on Generate Value Change Dump file script, specify the type of output signals to include, and

specify the top-level design instance name in your testbench.

4. Click Processing > Start Compilation.

5. Click Tools > Run EDA Simulation > EDA Gate Level Simulation. The Compiler creates the

<filename>_dump_all_vcd_nodes.tcl file, the ModelSim simulation <filename>_run_msim_gate_vhdl/

verilog.do file (including the .vcd and .tcl execution lines), and all other files for simulation. ModelSim

then automatically runs the generated .do to start the simulation.

6. Stop the simulation if your testbench does not have a break point. ModelSim generates the .vcd only

after simulation ends with the End Simulation function.

Viewing Simulation Waveforms

ModelSim-Altera, ModelSim, and QuestaSim automatically generate a Wave Log Format File (.wlf)

following simulation. You can use the .wlf to generate a waveform view.

Before you begin

To view a waveform from a .wlf through ModelSim-Altera, ModelSim, or QuestaSim, perform the

following steps:

1. Type vsim at the command line. The ModelSim/QuestaSim or ModelSim-Altera dialog box appears.

2. Click File > Datasets. The Datasets Browser dialog box appears.

3. Click Open and select your .wlf.

4. Click Done.

5. In the Object browser, select the signals that you want to observe.

6. Click Add > Wave, and then click Selected Signals.

You must first convert the .vcd to a .wlf before you can view a waveform in ModelSim-Altera,

ModelSim, or QuestaSim.

7. To convert the the .vcd to a .wlf, type the following at the command-line:

vcd2wlf <example>.vcd <example>.wlf

8. After conversion, view the .wlf waveform in ModelSim or QuestaSim.

You can convert your .wlf to a .vcd by using the wlf2vcd command

Simulating with ModelSim-Altera Waveform Editor

You can use the ModelSim-Altera Waveform Editor as a simple method to create stimulus vectors for

simulation. You can create this design stimulus via interactive manipulation of waveforms from the wave

window in ModelSim-Altera. With the ModelSim-Altera waveform editor, you can create and edit

waveforms, drive simulation directly from created waveforms, and save created waveforms into a stimulus

file.

Related Information

ModelSim Web Page

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Viewing Simulation Waveforms

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Mentor Graphics ModelSim and QuestaSim Support

Altera Corporation

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ModelSim Simulation Setup Script Example

The Quartus II software can generate a msim_setup.tcl simulation setup script for IP cores in your design.

The script compiles the required device library models, compiles the design files, and elaborates the

design with or without simulator optimization. To run the script, type source msim_setup.tcl in the

simulator Transcript window.

Alternatively, if you are using the simulator at the command line, you can type the following command:

vsim -c -do msim_setup.tcl

In this example the top-level-simulate.do custom top-level simulation script sets the hierarchy variable

TOP_LEVEL_NAME to top_testbench for the design, and sets the variable QSYS_SIMDIR to the location of

the generated simulation files.

# Set hierarchy variables used in the IP-generated files

set TOP_LEVEL_NAME "top_testbench"

set QSYS_SIMDIR "./ip_top_sim"

# Source generated simulation script which defines aliases used below

source $QSYS_SIMDIR/mentor/msim_setup.tcl

# dev_com alias compiles simulation libraries for device library files

dev_com

# com alias compiles IP simulation or Qsys model files and/or Qsys model files in

the correct order

com

# Compile top level testbench that instantiates your IP

vlog -sv ./top_testbench.sv

# elab alias elaborates the top-level design and testbench

elab

# Run the full simulation

run - all

In this example, the top-level simulation files are stored in the same directory as the original IP core, so

this variable is set to the IP-generated directory structure. The QSYS_SIMDIR variable provides the relative

hierarchy path for the generated IP simulation files. The script calls the generated msim_setup.tcl script

and uses the alias commands from the script to compile and elaborate the IP files required for simulation

along with the top-level simulation testbench. You can specify additional simulator elaboration command

options when you run the elab command, for example, elab +nowarnTFMPC. The last command run in

the example starts the simulation.

Unsupported Features

The Quartus II software does not support the following ModelSim simulation features:

• Altera does not support companion licensing for ModelSim AE.

• The USB software guard is not supported by versions earlier than Mentor Graphics ModelSim

software version 5.8d.

• For ModelSim-Altera software versions prior to 5.5b, use the PCLS utility included with the software

to set up the license.

• Some versions of ModelSim and QuestaSim support SystemVerilog, PSL assertions, SystemC, and

more. For more information about specific feature support, refer to Mentor Graphics literature

Related Information

• ModelSim-Altera Software Web Page

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ModelSim Simulation Setup Script Example

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Mentor Graphics ModelSim and QuestaSim Support

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