三星DDR3内存模块K4B2G1646F技术规格

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"三星DDR3-K4B2G1646F-BYMA是一款由三星电子生产的DDR3内存模块。" 三星的K4B2G1646F-BYMA是一款DDR3 SDRAM（Double Data Rate Third Generation Synchronous Dynamic Random-Access Memory）内存芯片，主要用于提升计算机系统的数据处理速度。DDR3内存相较于DDR2有更高的数据传输速率和更低的功耗，是DDR2内存的升级版本。这款内存芯片设计于2016年2月，遵循Rev.1.0的技术规范。产品规格方面，"K4B2G1646F"的型号标识可能意味着它具有以下特点： - "K4B"可能代表该内存芯片属于三星的一个特定产品系列。 - "2G"通常表示内存容量，这里指的是2GB，即2千兆字节的内存容量。 - "16"可能是指该内存芯片的位宽，即16位，这意味着它一次可以处理16位的数据。 - "46"可能是指内存芯片的某种内部配置或性能指标，具体含义可能需要查阅更详细的规格表。 - "F"可能是生产版本或者特性标记。 - "BYMA"可能是该内存模块的特定版本或制造批次代码。文档中提到，三星保留更改产品、信息和规格的权利，且所有提供的信息都是“按原样”提供的，没有提供任何明示或暗示的保修。这意味着购买者应关注最新的产品信息，因为三星可能会对产品进行改进或调整。此外，三星明确指出其产品不适用于生命支持、关键医疗、安全设备等应用，因为在这些领域产品故障可能导致生命或人身伤害。同样，这些产品也不适用于军事或国防应用，或受特殊条款和规定约束的政府采购项目。如果需要更新或更多关于三星产品的信息，用户应联系最近的三星办事处。文档还强调所有提及的品牌名称、商标和注册商标归各自所有者所有。 K4B2G1646F-BYMA是三星的一款DDR3内存芯片，具备2GB的容量，设计用于提高系统性能，但不适用于高风险应用。用户在使用时需注意其适用范围和更新信息。

- 12 -

datasheet DDR3L SDRAM

Rev. 1.0

K4B2G1646F

[ Table 9 ] Single-ended AC & DC input levels for DQ and DM (1.35V)

NOTE :

1. For input only pins except

RESET, V

REF

= V

REFDQ

(DC)

2.See "Overshoot and Undershoot specifications" section.

3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).

4. For reference: approx. VDD/2 +/- 13.5 mV.

5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V, the respective levels in JESD79-3 ( VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/

L.DQ(AC150), VIH/L.DQ(AC135), etc. ) apply. The 1.5 V levels (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135), etc. ) do not apply when the

device is operated in the 1.35 voltage range.

[ Table 10 ] Single-ended AC & DC input levels for DQ and DM (1.5V)

NOTE :

1. For input only pins except

RESET, V

REF

= V

REFDQ

(DC)

2.See "Overshoot and Undershoot specifications" section.

3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).

4. For reference: approx. VDD/2 +/- 15 mV.

5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)

6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)

7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC175) value is used when Vref + 0.175V is referenced,

VIH.DQ(AC150) value is used when Vref + 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced.

8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC175) value is used when Vref - 0.175V is referenced,

VIL.DQ(AC150) value is used when Vref - 0.150V is referenced, and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced.

9. V

REF

(DC) is measured relative to VDD at the same point in time on the same device

10. Optional in DDR3 SDRAM for DDR3-800/1066/1333/1600: Users should refer to the DRAM supplier data sheetand/or the DIMM SPD to determine if DDR3 SDRAM devices

support this option.

Symbol Parameter

DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866

Unit NOTE

Min. Max. Min. Max. Min. Max.

1.35V

IH.DQ

(DC90)

DC input logic high

REF

+ 90 V

REF

+ 90 V

REF

+ 90 V

mV 1

IL.DQ

(DC90)

DC input logic low

REF

- 90 V

REF

- 90 V

REF

- 90

mV 1

IH.DQ

(AC160)

AC input logic high

REF

+ 160

Note 2 - - - - mV 1,2,5

IL.DQ

(AC160)

AC input logic low Note 2

REF

- 160

- - - - mV 1,2,5

IH.DQ

(AC135)

AC input logic high

REF

+ 135

Note 2

REF

+ 135

Note 2 - - mV 1,2,5

IL.DQ

(AC135)

AC input logic low Note 2

REF

- 135

Note 2

REF

- 135

- - mV 1,2,5

IH.DQ

(AC130)

AC input logic high - - - -

REF

+ 130

Note 2 mV 1,2,5

IL.DQ

(AC130)

AC input logic low - - - - Note 2

REF

- 130

mV 1,2,5

REF

(DC)

Reference Voltage for DQ,

DM inputs

0.49*V

0.51*V

0.49*V

0.51*V

0.49*V

0.51*V

V 3,4

Symbol Parameter

DDR3-800/1066 DDR3-1333/1600 DDR3-1866

Unit NOTE

Min. Max. Min. Max. Min. Max.

1.5V

IH.DQ

(DC100)

DC input logic high

REF

+ 100 V

REF

+ 100 V

REF

+ 100 V

mV 1,5

IL.DQ

(DC100)

DC input logic low

REF

- 100 V

REF

- 100 V

REF

- 100

mV 1,6

IH.DQ

(AC175)

AC input logic high

REF

+ 175

NOTE 2 - - - - mV 1,2,7

IL.DQ

(AC175)

AC input logic low NOTE 2

REF

- 175

- - - - mV 1,2,8

IH.DQ

(AC150)

AC input logic high

REF

+ 150

NOTE 2

REF

+ 150

NOTE 2 - - mV 1,2,7

IL.DQ

(AC150)

AC input logic low NOTE 2

REF

- 150

NOTE 2

REF

- 150

- - mV 1,2,8

IH.DQ

(AC135)

AC input logic high

REF

+ 135

NOTE 2

REF

+ 135

NOTE 2

REF

+ 135

NOTE 2 mV 1,2,7,10

IL.DQ

(AC135)

AC input logic low NOTE 2

REF

- 135

NOTE 2

REF

- 135

NOTE 2

REF

- 135

mV 1,2,8,10

REF

(DC)

Reference Voltage for DQ,

DM inputs

0.49*V

0.51*V

0.49*V

0.51*V

0.49*V

0.51*V

V 3,4,9

- 15 -

datasheet DDR3L SDRAM

Rev. 1.0

K4B2G1646F

[ Table 12 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.35V)

NOTE: Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.

[ Table 13 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.5V)

NOTE : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VILdiff(ac)

level.

8.3.3 Single-ended requirements for differential signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for

single-ended signals.

CK and CK have to approximately reach V

SEH

min / V

SEL

max [approximately equal to the ac-levels { V

(AC) / V

(AC)} for ADD/CMD signals] in every

half-cycle.

DQS, DQSL, DQSU, DQS, DQSL have to reach V

SEH

min / V

SEL

max [approximately the ac-levels { V

(AC) / V

(AC)} for DQ signals] in every half-cycle

proceeding and following a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V

150(AC)/V

150(AC) is used for ADD/CMD sig-

nals, then these ac-levels apply also for the single-ended signals CK and

CK .

Slew Rate [V/ns]

DDR3L-800/1066/1333/1600 DDR3L-1866

tDVAC [ps] @ |V

IH/

Ldiff

(AC)| = 320mV

tDVAC [ps] @ |V

IH/

Ldiff

(AC)| = 270mV

tDVAC [ps]

@ |VIH/Ldiff(ac)|

=270mV

tDVAC [ps]

@ |VIH/Ldiff(ac)|

=250mV

tDVAC [ps]

@ |VIH/Ldiff(ac)|

=260mV

min max min max min max min max min max

> 4.0 189 - 201 - 163 - 168 - 176 -

4.0 189 - 201 - 163 - 168 - 176 -

3.0 162 - 179 - 140 - 147 - 154 -

2.0 109 - 134 - 95 - 105 - 111 -

1.8 91 - 119 - 80 - 91 - 97 -

1.6 69 - 100 - 62 - 74 - 78 -

1.4 40 - 76 - 37 - 52 - 56 -

1.2 note - 44 - 5 - 22 - 24 -

1.0 note - note - note - note - note -

< 1.0 note - note - note - note - note -

Slew Rate [V/ns]

DDR3-800/1066/1333/1600 DDR3-1866

tDVAC [ps]

@ V

IH/Ldiff

(AC)= 350mV

tDVAC [ps]

@ V

IH/Ldiff

(AC)= 300mV

tDVAC [ ps ]

@ VIH/L diff(ac)

=270mv

(DQS - DQS#) only

(Optional)

tDVAC [ps]

@ V

IH/Ldiff

(AC)

= 270mV

tDVAC [ps]

@ V

IH/Ldiff

(AC)

=250mV(CK - CK#) only

min max min max min max min max min max

> 4.0 75 - 175 - 214 - 134 - 139 -

4.0 57 - 170 - 214 - 134 - 139 -

3.0 50 - 167 - 191 - 112 - 118 -

2.0 38 - 119 - 146 - 67 - 77 -

1.8 34 - 102 - 131 - 52 - 63 -

1.6 29 - 81 - 113 - 33 - 45 -

1.4 22 - 54 - 88 - 9 - 23 -

1.2 note - 19 - 56 - note - note -

1.0 note - note - 11 - note - note -

< 1.0 note - note - note - note - note -

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