BCM56150：集成式24端口千兆以太网交换机规格概览

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本文档是关于博通(Broadcom)BCM56150型号系统级芯片(SoC)的规格书。BCM56150是一款针对边缘网络连接应用设计的24端口管理型千兆以太网交换机，它集成了四个10Gbps以太网上行链路、一个1GHz ARM Cortex-A9单核处理器以及16个铜线物理层(PHYs)。这款芯片在紧凑的29x29毫米封装下提供了高度集成，支持多种接口标准，包括Broadcom的HiGig2和HiGig+技术，以便于与SGMII、XFI和10GBASE-KR/CR/LR/SR等高速以太网标准相兼容。主要特点包括： 1. **集成度高**：BCM56150整合了16G PHYs和强大的中央处理单元(CPU)，显著减少了外部组件的需求，提高了系统效率和可靠性。 2. **高速接口**：提供四个10GBASE接口，支持最高10Gbps的数据传输速度，满足企业级L3管理网络交换机和服务提供商的MTU/MDU应用需求。 3. **多功能I/O配置**：该设备支持多种I/O速度选项（1G、2.5G、5G和10G），可适应不同场景下的边缘网络，如低成本的办公环境或对性能有更高要求的数据中心环境。 4. **应用广泛**：特别适合成本敏感的边缘网络应用，如企业级别的数据中心机房的交换机，或者服务提供商用于接入网的多租户单元(MDU)。 5. **小型化设计**：29mmx29mm的紧凑尺寸使得BCM56150在空间受限的环境中也能实现高效部署。 6. **技术支持**：文档提供者为Broadcom，地址位于加州尔湾，联系方式包括电话和传真，便于用户获取进一步的技术支持和更新。 BCM56150是一款高性能、高度集成的交换芯片，通过其独特的设计和丰富的功能，为边缘网络连接提供了强大而灵活的解决方案。对于关注成本效益、追求高速度和小型化的网络设备制造商来说，这款芯片是一个理想的选择。

7/23/2015 RTDSQ

List of TablesBCM56150 Data Sheet

BROADCOM CONFIDENTIAL

Broadcom

December 11, 2014 • 56150-DS06-R Page 16

Table 35: BSC Master/Slave Fast-Mode Timing............................................................................................ 123

Table 36: BSC Master/Slave Standard-Mode Timing .................................................................................... 123

Table 37: SPI Master Mode Timing ............................................................................................................... 124

Table 38: SPI Slave Fast Mode Timing ......................................................................................................... 125

Table 39: MDC/MDIO Timing......................................................................................................................... 126

Table 40: AC Characteristics for JTAG.......................................................................................................... 127

Table 41: NAND Flash Timing Characteristics for Command, Address, and Data Input ............................... 130

Table 42: NAND Flash Timing Characteristics .............................................................................................. 130

Table 43: Default NOR Flash Write Timing.................................................................................................... 131

Table 44: Default NOR Flash Read Timing ................................................................................................... 132

Table 45: BroadSync Input Timing: Slave Mode............................................................................................ 134

Table 46: BroadSync Output Timing: Master Mode ....................................................................................... 134

Table 47: L1_RCVRD_CLK and L1_RCVRD_CLK_BKUP Output Timing .................................................... 136

Table 48: L1_RCVRD_CLK_VALID AND L1_RCVRD_CLK Output Timing.................................................. 136

Table 49: QSPI BSPI Mode Master Interface Timing Specifications ............................................................. 137

Table 50: QSPI MSPI Mode Master Interface Timing Specifications............................................................. 138

Table 51: AC Specifications for the DDR3-1333 Interface ............................................................................ 140

Table 52: PCIE_REFCLK (HCSL) ................................................................................................................. 143

Table 53: PCIe_RX ........................................................................................................................................ 144

Table 54: PCIe_TX ........................................................................................................................................ 144

Table 55: LED Timing .................................................................................................................................... 145

Table 56: XTALP/XTALN Input Requirements............................................................................................... 146

Table 57: XG_PLL2_REFCLK Input Requirements....................................................................................... 147

Table 58: BS[1:0]_PLL_REFCLK Input Requirements ..................................................................................148

Table 59: TS_PLL_REFCLK Input Requirements ......................................................................................... 149

Table 60: LC_PLL1_REFCLK Input Requirements ....................................................................................... 150

Table 61: LC_PLL0_REFCLK Input Requirements ....................................................................................... 151

Table 62: EXT_QS2_CLKP/N Output Specifications..................................................................................... 152

Table 63: BS[1:0]_PLL_CLK Output Specifications....................................................................................... 153

Table 64: QSGMII TX .................................................................................................................................... 154

Table 65: QSGMII RX .................................................................................................................................... 155

Table 66: SGMII Serial Interface Output Timings .......................................................................................... 156

Table 67: SGMII Serial Interface Input Timings ............................................................................................. 157

Table 68: 2.5GbE/SerDes Interface Output Timings ..................................................................................... 157

Table 69: 2.5GbE/SerDes Interface Input Timings ........................................................................................ 158

Table 70: Warpcore Technology Serial Interface Operating Conditions........................................................ 159

Table 71: Serial Interface Receive Characteristics ........................................................................................ 159

7/23/2015 RTDSQ

Ethernet Switch ControllerBCM56150 Data Sheet

BROADCOM CONFIDENTIAL

Broadcom

December 11, 2014 • 56150-DS06-R Page 20

Ethernet Switch Controller

The Broadcom

BCM56150 integrates 16 GbE ports with embedded GPHYs and 8 GbE ports through QSGMII

interfaces and two TSC ports with flexible configuration as shown in Table 1 on page 19.

The BCM56150 is a highly integrated solution ideally suited for stand-alone GbE switches as well as stackable

GbE switches. The switch controller combines all the functions of a high-speed switch system, including packet

buffer, SerDes, media access controllers, address management, and a non-blocking switch fabric. The

BCM56150 device supports auto-DoS attack prevention and SNMP, IEEE 802.1x, Spanning Tree, and Rapid

Spanning Tree protocols.

The BCM56150:

• Provides 16 full-duplex GbE ports with embedded GPHYs.

• Provides two QSGMII interface to external PHYs for additional eight full-duplex GbE ports. These GbE

ports support both copper and fiber media (via external PHY device).

• Provides four stackable/uplink 10G ports.

• Supports 48-port GbE + four 10GbE non-blocking L3 switch design, using two BCM56150 devices.

• Integrates 1.5 MB internal memory in the Common Buffer Pool (CBP) for packet buffering.

• Provides hardware support for IPv4 and IPv6 protocols.

• Supports a Broadcom Serial control (BSC) controller for communicating with external devices such as

serial EEPROM, and Flash ROM devices.

• Supports a serial interface for the MII management (MDC/MDIO) of physical layer devices.

• Supports PCIe interface for external CPU host communication.

• Contains the memory needed to host L2 and L3 switching tables.

• Supports VLAN double-tagging.

• Supports advanced QoS shaping for service provider networks.

• ContentAware™ processing (via the Filter Processor (FP) feature) enables unmatched flexibility and

programmability. The ContentAware engine can be used for applications such as policy-based routing or

Access Control List (ACL) operation.

• Integrates sophisticated metering, statistics, and traffic management features, optimizing the QoS for

voice, video, and data convergence.

• Provides built-in security functions for highly secure enterprise network.

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