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Broadwell-DE SoC外部设计规格:核心与未核心寄存器
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更新于2024-07-06
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"544041_Broadwell_DE_EDS_Registers_Vol2_544041_v1_0.pdf 是一本关于 Broadwell-DE SoC 外部设计规范(External Design Specification,简称 EDS)的手册,主要涵盖了核心及非核心寄存器的详细信息。该手册由 Intel 公司于2014年7月发布,文档编号为544041,版本号1.0。"
本文档是 Broadwell-DE System-on-Chip (SoC) 设计的关键参考资料,主要针对的是 Volume Two:Core and Uncore Registers 部分,它是系列文档中的第五卷。 Broadwell-DE 是 Intel 推出的一款面向数据中心和高性能计算应用的处理器架构。这个处理器架构包含了高级微处理器的设计,包括中央处理器(CPU)核心和周边组件,如内存控制器、输入/输出接口等。
在手册中,读者可以找到关于 Broadwell-DE SoC 的核心寄存器和非核心寄存器的详细规格,这些信息对于系统开发者、硬件工程师以及驱动程序编写者来说至关重要。核心寄存器通常涉及 CPU 的核心功能,如指令执行、缓存管理、性能监控等,而非核心寄存器则与 CPU 的外围功能紧密相关,如电源管理、热控制、I/O 控制等。
手册明确指出,提供的信息与 Intel 产品相关,但不授予任何知识产权许可,除非在 Intel 产品的销售条款和条件中明确规定。Intel 对其产品不做任何形式的明示或暗示保证,包括但不限于对特定目的的适用性、商品质量和非侵权性的保证。对于那些可能导致人身伤害或死亡的“关键任务应用”,Intel 特别强调用户需自行承担风险,如果在这些应用中使用 Intel 产品,用户需同意赔偿 Intel 及其关联方免受任何损害。
这本 Broadwell-DE EDS 手册提供了深入的技术细节,对于理解并有效地利用 Broadwell-DE SoC 平台的硬件资源,进行系统级设计和优化,以及开发相应的软件支持是必不可少的参考资料。无论是硬件设计人员还是软件开发者,都需要仔细研究这本手册以确保他们的解决方案能够充分利用 Intel 的处理器技术,并满足安全性和性能的要求。
4.3.9 HDR...................................................................................................... 315
4.3.10 BIST....................................................................................................315
4.3.11 svid..................................................................................................... 316
4.3.12 sdid.....................................................................................................316
4.3.13 CAPPTR................................................................................................316
4.3.14 INTL.................................................................................................... 316
4.3.15 INTPIN.................................................................................................316
4.3.16 MINGNT............................................................................................... 316
4.3.17 MAXLAT............................................................................................... 317
4.3.18 pxpcap.................................................................................................317
4.3.19 dimmmtr_0.......................................................................................... 317
4.3.20 dimmmtr_1.......................................................................................... 318
4.3.21 amap...................................................................................................319
4.3.22 tadchnilvoffset_0...................................................................................320
4.3.23 tadchnilvoffset_1...................................................................................321
4.3.24 tadchnilvoffset_2...................................................................................321
4.3.25 tadchnilvoffset_3...................................................................................321
4.3.26 tadchnilvoffset_4...................................................................................322
4.3.27 tadchnilvoffset_5...................................................................................322
4.3.28 tadchnilvoffset_6...................................................................................323
4.3.29 tadchnilvoffset_7...................................................................................323
4.3.30 tadchnilvoffset_8...................................................................................323
4.3.31 tadchnilvoffset_9...................................................................................324
4.3.32 tadchnilvoffset_10................................................................................. 324
4.3.33 tadchnilvoffset_11................................................................................. 325
4.3.34 pxpenhcap............................................................................................325
4.3.35 rirwaynesslimit_0.................................................................................. 325
4.3.36 rirwaynesslimit_1.................................................................................. 326
4.3.37 rirwaynesslimit_2.................................................................................. 326
4.3.38 rirwaynesslimit_3.................................................................................. 326
4.3.39 rirwaynesslimit_4.................................................................................. 327
4.3.40 ririlv0offset_0....................................................................................... 327
4.3.41 ririlv1offset_0....................................................................................... 328
4.3.42 ririlv2offset_0....................................................................................... 328
4.3.43 ririlv3offset_0....................................................................................... 328
4.3.44 ririlv4offset_0....................................................................................... 329
4.3.45 ririlv5offset_0....................................................................................... 329
4.3.46 ririlv6offset_0....................................................................................... 329
4.3.47 ririlv7offset_0....................................................................................... 330
4.3.48 ririlv0offset_1....................................................................................... 330
4.3.49 ririlv1offset_1....................................................................................... 330
4.3.50 ririlv2offset_1....................................................................................... 331
4.3.51 ririlv3offset_1....................................................................................... 331
4.3.52 ririlv4offset_1....................................................................................... 331
4.3.53 ririlv5offset_1....................................................................................... 332
4.3.54 ririlv6offset_1....................................................................................... 332
4.3.55 ririlv7offset_1....................................................................................... 332
4.3.56 ririlv0offset_2....................................................................................... 333
4.3.57 ririlv1offset_2....................................................................................... 333
4.3.58 ririlv2offset_2....................................................................................... 333
4.3.59 ririlv3offset_2....................................................................................... 334
Broadwell-DE—Contents
Broadwell-DE SoC External Design Specification (EDS), Volume Two: Core and Uncore Registers
Volume 2 of 5 July 2014
16 Intel Confidential Doc. No.: 544041, Rev.: 1.0
4.3.60 ririlv4offset_2....................................................................................... 334
4.3.61 ririlv5offset_2....................................................................................... 334
4.3.62 ririlv6offset_2....................................................................................... 335
4.3.63 ririlv7offset_2....................................................................................... 335
4.3.64 ririlv0offset_3....................................................................................... 335
4.3.65 ririlv1offset_3....................................................................................... 336
4.3.66 ririlv2offset_3....................................................................................... 336
4.3.67 ririlv3offset_3....................................................................................... 336
4.3.68 ririlv4offset_3....................................................................................... 337
4.3.69 ririlv5offset_3....................................................................................... 337
4.3.70 ririlv6offset_3....................................................................................... 337
4.3.71 ririlv7offset_3....................................................................................... 338
4.3.72 ririlv0offset_4....................................................................................... 338
4.3.73 ririlv1offset_4....................................................................................... 338
4.3.74 ririlv2offset_4....................................................................................... 339
4.3.75 ririlv3offset_4....................................................................................... 339
4.3.76 ririlv4offset_4....................................................................................... 339
4.3.77 ririlv5offset_4....................................................................................... 340
4.3.78 ririlv6offset_4....................................................................................... 340
4.3.79 ririlv7offset_4....................................................................................... 340
4.3.80 rsp_func_addr_match_lo........................................................................ 340
4.3.81 rsp_func_addr_match_hi........................................................................ 341
4.3.82 rsp_func_addr_mask_lo......................................................................... 341
4.3.83 rsp_func_addr_mask_hi......................................................................... 341
4.3.84 rsp_func_rank_bank_match....................................................................342
4.4 Bus: 1, Device: 20, Function: 0, 1 (Channel[0-1])................................................... 342
4.4.1 VID....................................................................................................... 347
4.4.2 DID.......................................................................................................347
4.4.3 PCICMD................................................................................................. 347
4.4.4 PCISTS.................................................................................................. 348
4.4.5 RID....................................................................................................... 349
4.4.6 CCR...................................................................................................... 349
4.4.7 CLSR..................................................................................................... 349
4.4.8 PLAT..................................................................................................... 350
4.4.9 HDR...................................................................................................... 350
4.4.10 BIST....................................................................................................350
4.4.11 svid..................................................................................................... 350
4.4.12 sdid.....................................................................................................350
4.4.13 CAPPTR................................................................................................350
4.4.14 INTL.................................................................................................... 351
4.4.15 INTPIN.................................................................................................351
4.4.16 MINGNT............................................................................................... 351
4.4.17 MAXLAT............................................................................................... 351
4.4.18 pxpcap.................................................................................................351
4.4.19 pmoncntr_0..........................................................................................352
4.4.20 pmoncntr_1..........................................................................................352
4.4.21 pmoncntr_2..........................................................................................352
4.4.22 pmoncntr_3..........................................................................................352
4.4.23 pmoncntr_4..........................................................................................353
4.4.24 pmondbgcntresetval.............................................................................. 353
4.4.25 pmoncntr_fixed.....................................................................................353
Contents—Broadwell-DE
Broadwell-DE SoC External Design Specification (EDS), Volume Two: Core and Uncore Registers
July 2014 Volume 2 of 5
Doc. No.: 544041, Rev.: 1.0 Intel Confidential 17
4.4.26 pmoncntrcfg_0......................................................................................353
4.4.27 pmoncntrcfg_1......................................................................................354
4.4.28 pmoncntrcfg_2......................................................................................355
4.4.29 pmoncntrcfg_3......................................................................................356
4.4.30 pmoncntrcfg_4......................................................................................357
4.4.31 pmondbgctrl......................................................................................... 358
4.4.32 PMONCNTRCFGFIXED ...........................................................................359
4.4.33 pmonunitctrl......................................................................................... 360
4.4.34 pmonunitstatus..................................................................................... 360
4.4.35 pxpenhcap............................................................................................361
4.4.36 et_cfg..................................................................................................361
4.4.37 chn_temp_cfg.......................................................................................361
4.4.38 chn_temp_stat......................................................................................362
4.4.39 dimm_temp_oem_0...............................................................................362
4.4.40 dimm_temp_oem_1...............................................................................363
4.4.41 dimm_temp_th_0..................................................................................363
4.4.42 dimm_temp_th_1..................................................................................364
4.4.43 dimm_temp_thrt_lmt_0......................................................................... 364
4.4.44 dimm_temp_thrt_lmt_1......................................................................... 365
4.4.45 dimm_temp_ev_ofst_0.......................................................................... 365
4.4.46 dimm_temp_ev_ofst_1.......................................................................... 366
4.4.47 dimmtempstat_0...................................................................................366
4.4.48 dimmtempstat_1...................................................................................367
4.4.49 thrt_pwr_chnl....................................................................................... 368
4.4.50 pm_cmd_pwr_0.................................................................................... 368
4.4.51 pm_cmd_pwr_1.................................................................................... 369
4.4.52 et_dimm_avg_sum_0............................................................................ 369
4.4.53 et_dimm_avg_sum_1............................................................................ 370
4.4.54 et_dimm_th_0...................................................................................... 370
4.4.55 et_dimm_th_1...................................................................................... 370
4.4.56 thrt_pwr_dimm_0................................................................................. 370
4.4.57 thrt_pwr_dimm_1................................................................................. 371
4.4.58 thrt_count_dimm_0............................................................................... 371
4.4.59 thrt_count_dimm_1............................................................................... 371
4.4.60 pm_pdwn............................................................................................. 372
4.4.61 mc_term_rnk_msk................................................................................ 373
4.4.62 pm_sref............................................................................................... 373
4.4.63 pm_dll................................................................................................. 374
4.4.64 et_ch_avg............................................................................................ 375
4.4.65 et_ch_sum........................................................................................... 375
4.4.66 et_ch_th.............................................................................................. 375
4.4.67 tcdbp...................................................................................................375
4.4.68 tcrap................................................................................................... 376
4.4.69 tcrwp...................................................................................................376
4.4.70 tcothp..................................................................................................378
4.4.71 tcrfp.................................................................................................... 378
4.4.72 tcrftp................................................................................................... 379
4.4.73 tcsrftp..................................................................................................379
4.4.74 tcmr2shadow........................................................................................379
4.4.75 tczqcal................................................................................................. 380
4.4.76 tcstagger_ref........................................................................................ 380
Broadwell-DE—Contents
Broadwell-DE SoC External Design Specification (EDS), Volume Two: Core and Uncore Registers
Volume 2 of 5 July 2014
18 Intel Confidential Doc. No.: 544041, Rev.: 1.0
4.4.77 tcmr4shadow........................................................................................381
4.4.78 tcmr0shadow........................................................................................381
4.4.79 tcmr5shadow........................................................................................381
4.4.80 tcmr3shadow........................................................................................382
4.4.81 idletime............................................................................................... 382
4.4.82 rdimmtimingcntl....................................................................................383
4.4.83 rdimmtimingcntl2.................................................................................. 384
4.4.84 tcmrs...................................................................................................384
4.4.85 cpgc_pda_shadow................................................................................. 384
4.4.86 erf_ddr4_cmd_reg0............................................................................... 384
4.4.87 erf_ddr4_cmd_reg1............................................................................... 385
4.4.88 erf_ddr4_cmd_reg2............................................................................... 385
4.4.89 erf_ddr4_cmd_reg3............................................................................... 386
4.4.90 erf_ddr4_cmd_reg5............................................................................... 386
4.4.91 erf_ddr4_cmd_reg6............................................................................... 386
4.4.92 erf_ddr4_cmd_reg7............................................................................... 387
4.4.93 rd_odt_tbl0.......................................................................................... 387
4.4.94 rd_odt_tbl1.......................................................................................... 388
4.4.95 rd_odt_tbl2.......................................................................................... 388
4.4.96 erf_ddr4_cmd_reg4............................................................................... 389
4.4.97 wr_odt_tbl0..........................................................................................389
4.4.98 wr_odt_tbl1..........................................................................................390
4.4.99 wr_odt_tbl2..........................................................................................390
4.4.100 tclrdp.................................................................................................391
4.4.101 tclrdp1............................................................................................... 392
4.4.102 tcothp2.............................................................................................. 393
4.4.103 caparinj..............................................................................................393
4.4.104 tddr4................................................................................................. 394
4.4.105 wdbwm.............................................................................................. 394
4.4.106 sparing...............................................................................................395
4.4.107 wmm_read_config............................................................................... 395
4.4.108 cpgc_patwdbclctl................................................................................. 395
4.4.109 cpgc_inorder.......................................................................................396
4.4.110 cpgc_patcadbctl.................................................................................. 396
4.4.111 cpgc_patcadbmrs................................................................................ 397
4.4.112 cpgc_patcadbmuxctl............................................................................ 398
4.4.113 cpgc_patcadbmux0pb...........................................................................398
4.4.114 cpgc_patcadbmux1pb...........................................................................399
4.4.115 cpgc_patcadbmux2pb...........................................................................399
4.4.116 cpgc_patcadbmux3pb...........................................................................400
4.4.117 cpgc_patcadbclmux0lmn.......................................................................400
4.4.118 cpgc_patcadbclmux1lmn.......................................................................400
4.4.119 cpgc_patcadbclmux2lmn.......................................................................401
4.4.120 cpgc_patcadbclmux3lmn.......................................................................402
4.4.121 cpgc_patcadbwrpntr.............................................................................402
4.4.122 cpgc_patcadbprog0..............................................................................403
4.4.123 cpgc_patcadbprog1..............................................................................403
4.4.124 cpgc_miscrefctl................................................................................... 404
4.4.125 cpgc_misczqctl.................................................................................... 404
4.4.126 cpgc_miscodtctl...................................................................................405
4.4.127 cpgc_miscckectl.................................................................................. 406
Contents—Broadwell-DE
Broadwell-DE SoC External Design Specification (EDS), Volume Two: Core and Uncore Registers
July 2014 Volume 2 of 5
Doc. No.: 544041, Rev.: 1.0 Intel Confidential 19
4.4.128 cpgc_err_ctl........................................................................................406
4.4.129 cpgc_err_data0................................................................................... 407
4.4.130 cpgc_err_data1................................................................................... 407
4.4.131 cpgc_err_ecc...................................................................................... 407
4.4.132 cpgc_err_data0_s................................................................................ 408
4.4.133 cpgc_err_data1_s................................................................................ 408
4.4.134 cpgc_err_data2_s................................................................................ 408
4.4.135 cpgc_err_data3_s................................................................................ 409
4.4.136 cpgc_err_chunk...................................................................................409
4.4.137 cpgc_err_byte.....................................................................................409
4.4.138 cpgc_err_addr0................................................................................... 410
4.4.139 cpgc_err_addr1................................................................................... 411
4.4.140 cpgc_err_counter_overflow................................................................... 411
4.4.141 cpgc_err_nth...................................................................................... 411
4.4.142 cpgc_patwdbcl_rdsts............................................................................411
4.4.143 cpgc_err_counter0...............................................................................412
4.4.144 cpgc_err_counter0_s............................................................................412
4.4.145 cpgc_err_counter1...............................................................................412
4.4.146 cpgc_err_counter1_s............................................................................412
4.4.147 cpgc_err_counter2...............................................................................413
4.4.148 cpgc_err_counter2_s............................................................................413
4.4.149 cpgc_err_counter3...............................................................................413
4.4.150 cpgc_err_counter3_s............................................................................413
4.4.151 cpgc_err_counter4...............................................................................414
4.4.152 cpgc_err_counter4_s............................................................................414
4.4.153 cpgc_err_counter5...............................................................................414
4.4.154 cpgc_err_counter5_s............................................................................414
4.4.155 cpgc_err_counter6...............................................................................415
4.4.156 cpgc_err_counter6_s............................................................................415
4.4.157 cpgc_err_counter7...............................................................................415
4.4.158 cpgc_err_counter7_s............................................................................415
4.4.159 cpgc_err_counter8...............................................................................416
4.4.160 cpgc_err_counter8_s............................................................................416
4.4.161 cpgc_err_ecc_s................................................................................... 416
4.4.162 ddr4_cbit_parity..................................................................................416
4.4.163 mask_rpq0......................................................................................... 416
4.4.164 mask_rpq1......................................................................................... 417
4.4.165 mask_wpq.......................................................................................... 417
4.4.166 mcmnt_chkn_bit..................................................................................417
4.4.167 mcsched_chkn_bit............................................................................... 418
4.4.168 mcsched_chkn_bit2............................................................................. 419
4.5 Bus: 1, Device: 20, Function: 2 (Channel[0-1]).......................................................419
4.5.1 VID....................................................................................................... 421
4.5.2 DID.......................................................................................................422
4.5.3 PCICMD................................................................................................. 422
4.5.4 PCISTS.................................................................................................. 422
4.5.5 RID....................................................................................................... 423
4.5.6 CCR...................................................................................................... 423
4.5.7 CLSR..................................................................................................... 424
4.5.8 PLAT..................................................................................................... 424
4.5.9 HDR...................................................................................................... 424
Broadwell-DE—Contents
Broadwell-DE SoC External Design Specification (EDS), Volume Two: Core and Uncore Registers
Volume 2 of 5 July 2014
20 Intel Confidential Doc. No.: 544041, Rev.: 1.0
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