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TLV320AIC3104-Q1
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SLAS715B –JUNE 2010–REVISED FEBRUARY 2017
Product Folder Links: TLV320AIC3104-Q1
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9.3 Feature Description
9.3.1 Audio Data Converters
The TLV320AIC3104-Q1 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16
kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters also can operate at
different sampling rates in various combinations, which are described further as follows.
The data converters are based on the concept of an f
S(ref)
rate that is used internal to the part, and it is related to
the actual sampling rates of the converters through a series of ratios. For typical sampling rates, f
S(ref)
is either
44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with additional
restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and
also to enable high-quality playback of low-sampling-rate data, without high-frequency audible noise being
generated.
The sampling rate of the ADC and DAC can be set to f
S(ref)
/ NCODEC or 2 × f
S(ref)
/ NCODEC, with NCODEC
being 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6 for both the NDAC and NADC settings. In the TLV320AIC3104-Q1,
NDAC and NADC must be set to the same value, as the device only supports a common sample rate for the
ADC and DAC channels. Therefore NCODEC = NDAC = NADC, and this is programmed by setting the value of
bits D7 to D4 equal to the value of bits D3 to D0 in register 2, on page 0.
9.3.2 Stereo Audio ADC
The TLV320AIC3104-Q1 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times
oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8
kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC is in
operation, the device requires that an audio master clock be provided and appropriate audio clock generation be
set up within the device.
In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to
support the case where only mono record capability is required. In addition, both channels can be fully powered
or entirely powered down.
The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an
initial sampling rate of 128 f
S
to the final output sampling rate of f
S
. The decimation filter provides a linear phase
output response with a group delay of 17 / f
S
. The –3-dB bandwidth of the decimation filter extends to 0.45 f
S
and
scales with the sample rate (f
S
). The filter has minimum 75-dB attenuation over the stop band from 0.55 f
S
to 64
f
S
. Independent digital high-pass filters are also included with each ADC channel, with a corner frequency that
can be independently set.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog antialiasing filtering are very relaxed. The TLV320AIC3104-Q1 integrates a second-order
analog antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter,
provides sufficient antialiasing filtering without requiring additional external components.
The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to
59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that
only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on
the register programming (see page 0, registers 19 and 22). This soft-stepping ensures that volume control
changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on
power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the
gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled
by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part
after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When the ADC
power-down flag is no longer set, the audio master clock can be shut down.