TI LMK61E0M：高性能集成振荡器，具备低抖动与I2C配置功能

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Output

Control

Power Conditioning

VDD

EEPROMRegisters

SCL

SDA

od = open-drain

PLL

VCO: 4.6 GHz ~ 5.6 GHz

10 nF

Device

Control

ADD

Integrated

Oscillator

N Div

™ûfractional

3 = tri-state

Integer Div

GND

R Div

/1, /4

Doubler

x1, x2

OUT0

OUT1

LMK61E0M

www.ti.com.cn

ZHCSG16A –JANUARY 2017–REVISED MAY 2017

8 Detailed Description

8.1 Overview

The LMK61E0 is a programmable oscillator family that generates commonly used reference clocks. LMK61E0M

supports 3.3-V LVCMOS outputs with less than 1000-fs RMS max jitter in integer PLL and fractional PLL modes.

8.2 Functional Block Diagram

NOTE

Control blocks are compatible with 1.8-V, 2.5-V, and 3.3-V I/O voltage levels.

8.3 Feature Description

8.3.1 Device Block-Level Description

The LMK61E0 is an integrated oscillator that includes a 50-MHz crystal and a fractional PLL with integrated VCO

that supports a frequency range of 4.6 GHz to 5.6 GHz. The PLL block consists of a phase frequency detector

(PFD), charge pump, integrated passive loop filter, a feedback divider that can support both integer and fractional

values and a delta-sigma engine for noise suppression in fractional PLL mode. Completing the device is the

combination of an integer output divider and an LVCMOS output buffer. The PLL is powered by on-chip low

dropout (LDO) linear voltage regulators and the regulated supply network is partitioned such that the sensitive

analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs

provide isolation to the PLL from any noise in the external power supply rail. The device supports fine and coarse

frequency margining by changing the settings of the integrated oscillator and the output divider respectively.

5 4 3 2

Reg5

Bit Number (s)

R5.2

LMK61E0M

ZHCSG16A –JANUARY 2017–REVISED MAY 2017

www.ti.com.cn

Feature Description (continued)

8.3.2 Device Configuration Control

The LMK61E0 supports I

C programming interface where an I

C host can update any device configuration after

the device enables the host interface and the host writes a sequence that updates the device registers. Once the

device configuration is set, the host can also write to the on-chip EEPROM for a new set of power-up defaults

based on the configuration pin settings in the soft pin configuration mode.

8.3.3 Register File Reference Convention

Figure 4 shows the method that this document employs to refer to an individual register bit or a grouping of

the bit number second. The LMK61E0 contains 38 registers that are 8 bits wide. The register addresses and the

bit positions both begin with the number zero (0). The bit address is placed in brackets or after a period. The first

bit in the register file is address R0[0] or R0.0 meaning that it is located in Register 0 and is bit position 0. The

last bit in the register file is address R72[7] or R72.7 referring to the 8th bit of register address 72 (the 73rd

context.

Figure 4. LMK61E0 Register Reference Format

8.3.4 Configuring the PLL

The PLL in LMK61E0 can be configured to accommodate various output frequencies either through I

programming interface or, in the absence of programming the PLL defaults stored in EEPROM are loaded on

power up. The PLL can be configured by setting the Reference Doubler, Integrated PLL Loop Filter, Feedback

Divider, and Output Divider. The corresponding register addresses and configurations are detailed in the

description section of each block below.

For the PLL to operate in closed-loop mode, the following condition in Equation 1 has to be met.

VCO

= F

REF

× (D/R) × [(INT + NUM/DEN)]

where

• F

VCO

: PLL/VCO Frequency (4.6 GHz to 5.6 GHz)

• F

REF

: 50-MHz reference input

• D: Reference input doubler, 1=Disabled, 2=Enabled

• R: Reference input divider, 1=Divider bypass, 4=Divide-by-4

• INT: PLL feedback divider integer value (12 bits, 1 to 4095)

• NUM: PLL feedback divider fractional numerator value (22 bits, 0 to 4194303)

• DEN: PLL feedback divider fractional denominator value (22 bits, 1 to 4194303) (1)

On LMK61E0M, the output frequency is related to the VCO frequency as given in Equation 2.

OUT

= F

VCO

/ (P × OUTDIV)

where

• P: VCO post-divider value, selectable between 4 or 5

• OUTDIV: Output divider value (9 bits, 6 to 256) (2)

The output frequency step size for every bit change in the numerator of the PLL fractional feedback divider is

given in Equation 3.

STEPSIZE = (F

REF

× D)/ (R × P × OUTDIV × DEN) (3)

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