新型n-和p型陡峭亚阈值斜坡隧道场效应晶体管

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"这篇论文主要介绍了基于异质结构Si/SiGe衬底的新型n型和p型隧道场效应晶体管（Tunnel-FET），这些器件展现出极小的亚阈值摆幅和低阈值电压，旨在实现低功耗和高能效的数字电路。" 在当前的微电子技术中，降低亚阈值摆幅（Subthreshold Swing）和阈值电压（Threshold Voltage）是提升集成电路能效的关键因素。传统的MOSFET（金属氧化物半导体场效应晶体管）在亚阈值区的电流控制效率较低，不利于低功耗应用。而隧道场效应晶体管（Tunnel-FET）则利用量子隧穿效应，能在更低电压下切换状态，从而显著降低功耗。该论文提出的n型和p型Tunnel-FET采用了Si/SiGe异质结构的通道层，这种设计可以有效改善器件的性能。通过理论分析和仿真优化，研究人员研究了改善器件特性的设计参数。这些新型T-FET的关闭状态电流（OFF current）极低，达到1fA/μm级别，同时通过设计，使其开启状态电流（ON current）显著高于先前报道的T-FET器件。亚阈值摆幅是指晶体管在亚阈值区的电流随栅极电压变化的斜率，通常以每十倍对数增加所需的电压差来衡量。在这些新型T-FET中，实现了低至15mV/dec的亚阈值摆幅，这是一个显著的突破，因为它意味着在低电压下即可实现良好的开关性能。此外，这些器件的阈值电压低至0.13V，这进一步降低了操作电源的需求，对于构建低功耗电路至关重要。论文还指出，这些T-FET设计的目标是与现有的CMOS（互补金属氧化物半导体）数字电路兼容，这意味着它们能够无缝集成到现有的集成电路设计中，而无需大规模改变制造工艺。这种兼容性是推动Tunnel-FET技术在实际应用中取代或补充现有MOSFET技术的重要一步。这篇论文的贡献在于提出了新型的n型和p型Tunnel-FET设计，通过优化的异质结构和器件参数，实现了亚阈值摆幅和阈值电压的显著降低，为未来低功耗、高能效的数字电路提供了新的可能。这种技术的发展将对微电子领域，尤其是物联网、移动设备和嵌入式系统等依赖低功耗解决方案的领域产生深远影响。

2752 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 11, NOVEMBER 2009

Steep Subthreshold Slope n- and p-Type Tunnel-FET

Devices for Low-Power and Energy-Efﬁcient

Digital Circuits

Yasin Khatami, Student Member, IEEE, and Kaustav Banerjee, Senior Member, IEEE

Abstract—In this paper, novel n- and p-type tunnel ﬁeld-effect

transistors (T-FETs) based on heterostructure Si/intrinsic–SiGe

channel layer are proposed, which exhibit very small subthreshold

swings, as well as low threshold voltages. The design parameters

for improvement of the characteristics of the devices are studied

and optimized based on the theoretical principles and simulation

results. The proposed devices are designed to have extremely

low

OFF currents on the order of 1 fA/μ m and engineered to

exhibit substantially higher

ON currents compared with previously

reported T-FET devices. Subthreshold swings as low as 15 mV/dec

and threshold voltages as low as 0.13 V are achieved in these

devices. Moreover, the T-FETs are designed to exhibit input and

output characteristics compatible with CMOS-type digital-circuit

applications. Using the proposed n- and p-type devices, the im-

plementation of an inverter circuit based on T-FETs is reported.

The performance of the T-FET-based inverter is compared with

the 65-nm low-power CMOS-based inverter, and a gain of ∼10

is achieved in static power consumption for the T-FET-based

inverter with smaller gate delay.

Index Terms—Band-to-band (B2B) tunneling, energy-efﬁcient

device, low power (LP), sub-kT/q device, subthreshold swing,

tunnel ﬁeld-effect transistor (T-FET).

I. INTRODUCTION

TEEP subthreshold-slope or small subthreshold-swing de-

vices are of great interest and signiﬁcance in light of

increasing subthreshold leakage current, which constitutes a

major concern not only for power dissipation of digital ICs but

also for their energy efﬁciency. As MOSFETs are scaled below

45 nm, the phenomenon of subthreshold leakage becomes

more signiﬁcant because of short-channel effects and increasing

parameter variations [1], as well as strong coupling between

temperature and subthreshold leakage current [2].

The leakage power is strongly inﬂuenced by the subthreshold

swing of a device deﬁned as S = (d log I

/dV

)

−1

, where

is the drain-to-source current under an applied gate-to-

source voltage V

.TheS indicates the minimum amount of

gate-voltage reduction necessary to lower the subthreshold cur-

rent by a factor of ten. Fig. 1 shows the minimum reported val-

ues of S for various classical and nonclassical CMOS, as well

Manuscript received November 8, 2008; revised August 3, 2009. Current

version published October 21, 2009. This work was supported in part by Intel

Corporation. The review of this paper was arranged by Editor V. R. Rao.

The authors are with the Department of Electrical and Computer Engineer-

ing, University of California, Santa Barbara, CA 93106 USA (e-mail: yasin@

ece.ucsb.edu; kaustav@ece.ucsb.edu).

Color versions of one or more of the ﬁgures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identiﬁer 10.1109/TED.2009.2030831

Fig. 1. Subthreshold swings (S) reported for various CMOS and emerg-

ing solid-state devices. CMOS devices show S ≥ 60 mV/dec. The proposed

T-FETs, T-CNFET, and IMOS devices exhibit the smallest values of S.

as nonsilicon solid-state devices [3]–[7]. It can be observed

that all of the CMOS-based transistors [Bulk, FinFET, and

fully-depleted silicon-on-insulator (FDSOI)] have S values

≥ 60 mV/dec (= 2.3 kT/q) at room temperature, while the

nanowire ﬁeld-effect transistor (NWFET) [4], the carbon-

nanotube-based tunnel ﬁeld-effect transistor (T-CNFET) [6],

[7], and the impact-ionization MOS-based transistor (IMOS)

[5] have lower values of S (sub-kT/q). However, these devices

suffer from difﬁculties in chip implementation, in terms of

fabrication process or high-voltage requirements for operation.

Among the new generations of sub-kT/q transistors, T-FET is

a promising device due to its low

OFF current [8]–[22] and in-

tegrability with CMOS process. It has been shown that T-FETs

exhibit subthreshold swing smaller than 60 mV/dec [8]–[22].

Moreover, it has been shown that T-FETs can be scaled down to

20 nm in channel length, without much degradation of the sub-

threshold slope, I

and I

OFF

[7], [12], [14]. However, T-FETs

have lower ON currents and higher threshold voltages compared

with MOSFETs. Although different T-FET structures have been

reported in the literature [9], [10], [19], and a vertical n-type

T-FET has been proposed in [12] and [16] to improve I

and S, and an n-type double-gate T-FET using high-k material

is proposed in [13] to improve performance, the

ON currents

reported in these works are well below that of CMOS, or

they exhibit threshold voltages higher than 0.4 V. Moreover, as

discussed in Section III-C, the reported p-type T-FETs usually

require gate voltages larger than the power-supply voltage to

operate [7], [15], [17], [21], which makes them difﬁcult to

be integrated in digital circuits. Circuit implementation of the

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