"JESD204C.1 英文资料下载：JEDEC标准序列接口协议更新"。

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The JESD204B-C protocol, also known as JEDEC STANDARD Serial Interface for Data Converters, is a key document that outlines the standards and guidelines for data converters. This protocol, updated in December 2021 under the revision JESD204C.1, is a crucial resource for engineers and developers working in the field of data conversion. The JESD204B-C protocol, available in English, is a comprehensive document produced by the JEDEC SOLID STATE TECHNOLOGY ASSOCIATION. It covers various aspects of data converter interfacing, including electrical and mechanical specifications, system connections, and data transfer protocols. The protocol is designed to ensure compatibility and interoperability between different data converter devices, enabling seamless integration into a wide range of applications. JEDEC standards and publications, including the JESD204B-C protocol, undergo a rigorous review and approval process by the JEDEC Board of Directors and legal counsel. This ensures that the information presented in these documents is accurate, reliable, and up-to-date. Engineers and developers can rely on the JESD204B-C protocol as a trusted resource for designing and implementing data converter interfaces in their projects. Overall, the JESD204B-C protocol is an essential resource for anyone working with data converters. It provides the necessary guidelines and specifications to ensure proper interfacing, communication, and data transfer between different devices. By following the standards outlined in the protocol, engineers can maximize the performance and reliability of their data converter systems, ultimately leading to successful and efficient project implementations.

JEDEC Standard No. 204C.01

Page 1

SERIAL INTERFACE FOR DATA CONVERTERS

(From JEDEC Board Ballot JCB-21-56, formulated under cognizance of the JEDEC JC-16 Committee on

Interface Technology.)

Scope 1

This standard describes a serialized interface between data converters and logic devices. It contains

normative information to enable designers to implement devices that communicate with other devices

covered by this specification. Informative annexes are included to clarify and exemplify the document.

Due to the range of applications involved, the intention of this standard is to completely specify only the

serial data interface and the link protocol. Certain signals common to both the interface and the function

of the device, such as device clocks and control interfaces, have application-dependent requirements. The

JESD204 standard does not require a specific implementation of the control interface, however a serial

interface is the recommended implementation. Devices may also have application-dependent modes, such

as a low power / shutdown mode that will affect the interface. In these instances, the specification merely

constrains other device properties as they relate to the interface, and leaves the specific implementation up

to the designer.

Revision A of the standard was expanded to support serial data interfaces consisting of single or multiple

lanes per converter device. In addition, converter functionality (ADC or DAC) can be distributed over

multiple devices:

• All parallel running devices are implemented or specified to run synchronously with each other

using the same data format.

• Normally this means that they are part of the same product family.

Revision B of the standard supports the following additional functions:

• Mechanism for achieving repeatable, programmable deterministic delay across the JESD204 link.

• Support for serial data rates up to 12.5 Gbps.

• Transition from using frame clock as the main clock source to using device clock as the main

clock source. Device clock frequency requirements offer much more flexibility compared to

requiring a frame clock input.

Revision C of the standard now supports the following additional functions:

• Data interfaces up to 32

.45 Gbps.

• Three link layers – 64B/66B, 64B/80B, and 8B/10B. The 8B/10B link layer is similar to the link

layer defined in JESD204B.

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JEDEC Standard No. 204C.01

Page 3

Normative references 2

The following normative documents contain provisions that, through reference in this text, constitute

provisions of this standard. For dated references, subsequent amendments to, or revisions of, any of these

publications do not apply. However, parties to agreements based on this standard are encouraged to

investigate the possibility of applying the most recent editions of the normative documents indicated

below. For undated references, the latest edition of the normative document referred to applies.

1. JEDEC JESD99, Terms, Definitions, and Letter Symbols for Microelectronic Devices.

2. IEEE Standard for Ethernet, IEEE Std. 802.3™-2018 section 3, clause 36, Physical Coding Sublayer

(PCS) and Physical Medium Attachment (PMA) sublayer, type 1000BASE-X.

https://standards.ieee.org/standard/802_3-2018.html

3. IEEE Standard for Ethernet, IEEE Std. 802.3™-2018 section 4, annex 48A, Jitter test patterns.

https://standards.ieee.org/standard/802_3-2018.html

4. OIF-SxI-5-01.0, System Interface Level 5 (SxI-5): Common Electrical Characteristics for 2.488 –

3.125 Gbps Parallel Interfaces, Optical Internetworking Forum, October 2002.

http://www.oiforum.com/wp-content/uploads/OIF-SxI5-01.0.pdf

5. OIF-CEI-04.0, Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for

6G+ bps and 11G+ bps and 25G+ bps I/O, Optical Internetworking Forum, February 18, 2017

04.0http://www.oiforum.com/wp-content/uploads/OIF_CEI_04.0.pdf

6. INCITS TR-35-2004 (R2009), Fibre Channel - Methodologies for Jitter and Signal Quality

Specification (FC-MJSQ), available from http://webstore.ansi.org

7. INCITS 450-2009, Information technology - Fibre Channel - Physical Interface - 4 (FC-PI-4), Annex

F, Scrambled test patterns. Available from http://webstore.ansi.org

8. INCITS TR-46-2011, Information technology - Fibre Channel - Methodologies for Signal Quality

Specification (FC-MSQS), clause 9, Test patterns. Available from http://webstore.ansi.org

For readability and ease-of-use of this specification, in some cases complete clauses, figures and/or tables

of reference standards have been copied (with permission) verbatim; for proper attribution and ease of

(cross)referencing, the original clause, table and/or, figure is indicated directly and the phrase “Reprinted”

is used (for example, Figure 22) In some other cases, the content of the original clause, table and/or figure

has been used as the starting point of the material in this specification, but has been modified (some

portions may have been deleted, phrasing modified, content augmented, etc.) so as to better fit the

intended application. In these cases, the original material is indicated preceded by the phrases “Based on”

or “Adapted and reprinted” (for example 5.2.3.1). In all cases, appropriate copyright holders are indicated.

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JEDEC Standard No. 204C.01

Page 5

3.1 Terms and definitions (cont’d)

clock generator: A circuit used to generate synchronous, phase aligned device clocks to various devices

in the JESD204 system.

NOTE A clock generator circuit can include one or more clock generator devices, but they must use a common

source clock.

code group: A set of ten bits that, when representing data, conveys an octet (applies to 8B/10B encoding,

see IEEE Std. 802.3 [5].)

command channel: Data stream using extra bandwidth afforded from sync headers (see 7.3.7.)

control interface: An application-specific interface used to pass information (usually status and control

information) between a converter device and a logic device and/or between a device and a higher layer

application level.

NOTE The JESD204 specification does not require a specific implementation of the control interface, however a

serial interface is the recommended implementation.

converter: An analog-to-digital converter (ADC) or digital-to-analog converter (DAC).

NOTE In this standard, a converter is assumed to interface via a single stream of digital samples.

converter device: A component package containing one or more converters.

NOTE This standard specifies the interactions between one logic device and one or more converter devices.

DAC device: A device containing one or more digital-to-analog converters connected to the JESD204

link.

DAC link: A link from a DAC device to a logic device.

data link: An assembly that is controlled by a link protocol enabling data to be transferred from a data

source to a data sink and consists of parts of two devices and the interconnecting data circuit, that is

(“terminal” replaced by “device” in Ref. ATIS Telecom Glossary [1].)

data rate: speed at which data is transferred measured in bits per second, denoted by the symbol 



descrambler: The inverse of a scrambler. (Ref. ATIS Telecom Glossary [1].)

NOTE The descrambler output is a signal restored to the state that it had when it entered the associated scrambler,

provided that no errors have occurred.

device clock: A main clock signal from which a device must generate its local clocks.

digital-to-analog converter: A circuit converting a digital sampled data stream to an analog signal. If the

analog signal is converted from a complex data stream, the DAC is defined as the subblock accepting

either the real or the imaginary component of the data stream.

EMB_LOCK: A state asserting that extended multiblock alignment has been achieved.

extended multiblock: A set of data containing one or more multiblocks.

fill bit: A bit used to artificially extend the block size in 64B/80B encoding mode.

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