ADRV9009: 集成双RF发射机与接收机数据表

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"ADI RFIC ADRV9009是一款集成了双RF发射器、接收器和观测接收器的高性能射频集成电路，适用于5G通信等领域。该器件的主要特性包括宽广的接收带宽、可调谐发射机合成带宽以及全集成的分数-N射频合成器和时钟合成器。此外，它还支持多芯片相位同步，确保RF本地振荡器和基带时钟的精确同步。" ADI公司的ADRV9009是一款先进的射频集成电路（RFIC），设计用于处理复杂的无线通信任务，尤其是在5G网络中。这款器件的独特之处在于它集成了双RF发射器和接收器，能够同时处理两个独立的无线信号路径，这在多模、多频段通信系统中非常有用。 1. **双RF发射器与接收器**：ADRV9009拥有两个独立的发射通道和接收通道，可以支持多种不同的无线标准和频率，提供灵活的系统设计。每个通道都具有高性能和高效率，能够在不同的通信模式下提供稳定的操作。 2. **双输入共享观测接收器**：这个特性使得ADRV9009能监控和分析接收信号的质量，帮助系统进行故障检测和信道状态信息的获取，从而优化通信性能。 3. **最大接收带宽200MHz**：这意味着ADRV9009能够处理高达200MHz带宽的接收信号，适应高速数据传输的需求，尤其对于5G NR（新空口）等高速通信标准至关重要。 4. **最大可调谐发射机合成带宽450MHz**：ADRV9009的发射机部分可以覆盖广泛的频率范围，允许快速切换到不同的工作频段，以满足不同应用场景的要求。 5. **最大观测接收器带宽450MHz**：观测接收器的宽带能力使其能够捕获和分析宽频带信号，这对于射频系统的调试和故障排除非常有用。 6. **全集成的分数-N射频合成器**：这种合成器提供高度精确的频率生成，支持窄带和宽带应用，同时降低功耗和占用空间。 7. **全集成的时钟合成器**：时钟是所有数字系统的心脏，ADRV9009内置的时钟合成器确保了系统的时序精度，对于高速数据处理至关重要。 8. **多芯片相位同步**：ADRV9009支持RF本地振荡器（LO）和基带时钟的相位同步，确保在多芯片系统中的信号一致性，这对于减少干扰和提高链路质量至关重要。 ADRV9009是一款全面的射频解决方案，适用于需要高性能、高灵活性和精确同步的5G通信系统。其创新的设计和功能体现了ADI公司在射频集成电路领域的领先地位，为现代无线通信提供了坚实的技术基础。

ADRV9009 Data Sheet

Rev. B | Page 16 of 127

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDDA1P3

to VSSA −0.3 V to +1.4 V

VDDD1P3_DIG to VSSD

−0.3 V to +1.4 V

VDD_INTERFACE to VSSA −0.3 V to +3.0 V

VDDA_3P3 to VSSA −0.3 V to +3.9 V

VDDA1P8_TX to VSSA −0.3 V to +2.0 V

VDD_INTERFACE Logic Inputs and

Outputs to VSSD

−0.3 V to VDD_

INTERFACE + 0.3 V

JESD204B Logic Outputs to VSSA

−0.3 V to

VDDA1P3_SER

JESD204B Logic Inputs to VSSA −0.3 V to

VDDA1P3_DES +0.3 V

Input Current to any Pin Except

Supplies

±10 mA

Maximum Input Power into RF Port 23 dBm (peak)

Maximum Transmitter Voltage

Standing Wave Ratio (VSWR)

3:1

Maximum T

110°C

Storage Temperature Range −65°C to +150°C

VDDA1P3 refers to all analog 1.3 V supplies.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

REFLOW PROFILE

The ADRV9009 reflow profile is in accordance with the JEDEC

JESD204B criteria for Pb-free devices. The maximum reflow

temperature is 260°C.

THERMAL MANAGEMENT

The ADRV9009 is a high power device that can dissipate over

3 W depending on the user application and configuration.

Because of the power dissipation, the ADRV9009 uses an

exposed die package to provide the customer with the most

effective method of controlling the die temperature. The exposed

die allows cooling of the die directly. Figure 5 shows the profile

view of the device mounted to a user printed circuit board (PCB)

and a heat sink (typically the aluminum case) to keep the junction

(exposed die) below the maximum T

detailed in Table 3. The

device is designed for a lifetime of 10 years when operating at

the maximum T

THERMAL RESISTANCE

Thermal performance is directly linked to PCB design and

operating environment. Careful attention to PCB thermal

design is required.

is the natural convection junction to ambient thermal

resistance measured in a circuit board for surface-mount

packages.

JC_TOP

is the conduction thermal resistance from junction to case

where the case temperature is measured at the top of the package.

Thermal resistance data for the ADRV9009 mounted on both a

JEDEC 2S2P test board and a 10-layer Analog Devices, Inc.,

evaluation board is listed in Table 4. Do not exceed the absolute

maximum T

rating in Table 3. Ten-layer PCB entries refer to the

10-layer Analog Devices evaluation board, which more

accurately reflects the PCB used in customer applications.

Table 4. Thermal Resistance

1, 2

Package Type θ

JC_TOP

Unit

BC-196-13 21.1 0.04 4.9 0.3 4.9

°C/W

For the θ

test, 100 µm thermal interface material (TIM) is used. TIM is

assumed to have 3.6 thermal conductivity watts/(meter × Kelvin).

Using enhanced heat removal techniques such as PCB, heat sink, and airflow

improves the thermal resistance values.

ESD CAUTION

CUSTOMER CASE (HEAT SINK)

CUSTOMER THERMAL FILLER

SILICON (DIE)

PACKAGE SUBSTRATE

CUSTOMER PCB

16499-008

igure 5. Typical Thermal Management Solution

Data Sheet ADRV9009

Rev. B | Page 17 of 127

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1234567891011121314

VSSA ORX2_IN+ ORX2_IN– VSSA RX2_IN+ RX2_IN– VSSA VSSA RX1_IN+ RX1_IN– VSSA ORX1_IN+ ORX1_IN– VSSA

VDDA1P3_

RX_RF

VSSA VSSA VSSA VSSA VSSA

RF_EXT_

LO_I/O–

RF_EXT_

LO_I/O+

VSSA VSSA VSSA VSSA VSSA VSSA

GPIO_3P3_0 GPIO_3P3_3

VDDA1P3_

RX_TX

VSSA

VDDA1P3_

RF_VCO_LDO

VDDA1P3_

RF_VCO_LDO

VDDA1P1_

RF_VCO

VDDA1P3_

RF_LO

VSSA

VDDA1P3_

AUX_VCO_

LDO

VSSA VDDA_3P3 GPIO_3P3_9 RBIAS

GPIO_3P3_1 GPIO_3P3_4 VSSA VSSA VSSA VSSA VSSA VSSA VSSA

VDDA1P1_

AUX_VCO

VSSA VSSA GPIO_3P3_8 GPIO_3P3_10

GPIO_3P3_2 GPIO_3P3_5 GPIO_3P3_6 VDDA1P8_BB VDDA1P3_BB VSSA REF_CLK_IN+ REF_CLK_IN– VSSA

AUX_SYNTH_

OUT

AUXADC_3 VDDA1P8_TX GPIO_3P3_7 GPIO_3P3_11

VSSA VSSA AUXADC_0 AUXADC_1 VSSA VSSA VSSA VSSA VSSA VSSA AUXADC_2 VSSA VSSA VSSA

VSSA VSSA VSSA VSSA

VDDA1P3_

CLOCK_ SYNTH

VSSA

VDDA1P3_

RF_SYNTH

VDDA1P3_

AUX_SYNTH

RF_SYNTH_

VTUNE

VSSA VSSA VSSA VSSA VSSA

TX2_OUT– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA TX1_OUT+

TX2_OUT+ VSSA GPIO_18 RESET

GP_

INTERRUPT

TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA TX1_OUT–

VSSA VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CS GPIO_14 GPIO_9 VSSA VSSA

VSSA VSSA SYNCIN1– SYNCIN1+ GPIO_6 GPIO_7 VSSD

VDDD1P3_

DIG

VDDD1P3_

DIG

VSSD GPIO_15 GPIO_8 SYNCOUT1– SYNCOUT1+

VDDA1P1_

CLOCK_VCO

VSSA SYNCIN0– SYNCIN0+ RX1_ENABLE TX1_ENABLE RX2_ENABLE TX2_ENABLE VSSA GPIO_17 GPIO_16

VDD_

INTERFACE

SYNCOUT0– SYNCOUT0+

VDDA1P3_

CLOCK_

VCO_LDO

VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSA

VDDA1P3_

SER

VDDA1P3_

DES

SERDIN1– SERDIN1+ SERDIN0– SERDIN0+ VSSA

AUX_SYNTH_

VTUNE

VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+

VDDA1P3_

SER

VDDA1P3_

DES

VSSA SERDIN3– SERDIN3+ SERDIN2– SERDIN2+

ADRV9009

16499-900

Figure

6. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Type Mnemonic Description

A1, A4, A7, A8, A11, A14, B2 to

B6, B9 to B14, C4, C9, C11,

D3 to D9, D11, D12, E6, E9,

F1, F2, F5 to F10, F12 to

F14, G1 to G4, G6, G10 to

G14, H2 to H10, H13, J2,

J13, K1, K2, K13, K14, L1, L2,

M2, M9, N2, N7, N14, P2,

P3, P10

Input VSSA Analog Supply Voltage (V

A2, A3 Input ORX2_IN+, ORX2_IN−

Differential Input for Observation Receiver 2. When unused, connect

these pins to ground.

ADRV9009 Data Sheet

Rev. B | Page 18 of 127

Pin No. Type Mnemonic Description

A5, A6 Input RX2_IN+, RX2_IN−

Differential Input for Main Receiver 2. When unused, connect these pins

to ground.

A9, A10 Input RX1_IN+, RX1_IN−

Differential Input for Main Receiver 1. When unused, connect these

pins to ground.

A12, A13 Input ORX1_IN+, ORX1_IN−

Differential Input for Observation Receiver 1. When unused, connect

these pins to ground.

B1 Input VDDA1P3_RX_RF Observation Receiver Supply.

B7, B8 Input

RF_EXT_LO_I/O−,

RF_EXT_LO_I/O+,

Differential External LO Input/Output. If these pins are used for the

external LO, the input frequency must be 2× the desired carrier

frequency. When unused, do not connect these pins.

Input/

output

GPIO_3P3_0

GPIO Pin Referenced to 3.3 V Supply. The alternate function is AUXDAC_4.

Because this pin contains an input stage, the voltage on the pin must

be controlled. When unused, this pin can be tied to ground through a

resistor (to safeguard against misconfiguration), or this pin can be left

floating, programmed as outputs, and driven low.

Input/

output

GPIO_3P3_3

GPIO Pin Referenced to 3.3 V Supply. Because this pin contains an input

stage, the voltage on the pin must be controlled. When unused, this pin

can be tied to ground through a resistor (to safeguard against

misconfiguration), or these pins can be left floating, programmed as

outputs, and driven low.

C13

Input/

output

GPIO_3P3_9

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_9. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

Input/

output

GPIO_3P3_1

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_5. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

Input/

output

GPIO_3P3_4

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_6. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

D13

Input/

output

GPIO_3P3_8

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_1. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

D14

Input/

output

GPIO_3P3_10

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_0. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

Input/

output

GPIO_3P3_2

GPIO Pin Referenced to 3.3 V Supply. Because this pin contains an input

stage, the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor (to safeguard against

misconfiguration), or these pins can be left floating, programmed as

outputs, and driven low.

Input/

output

GPIO_3P3_5

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_7. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

Input/

output

GPIO_3P3_6

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_8. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

Data Sheet ADRV9009

Rev. B | Page 19 of 127

Pin No. Type Mnemonic Description

E13

Input/

output

GPIO_3P3_7

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_2. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

E14

Input/

output

GPIO_3P3_11

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_3. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

C3 Input VDDA1P3_RX_TX

1.3 V Supply for Transmitter/Receiver Baseband Circuits, Transimpedance

Amplifier (TIA), Transmitter Transconductance (GM), Baseband Filters,

and Auxiliary DACs.

C5, C6 Input VDDA1P3_RF_VCO_LDO

RF VCO LDO Supply Inputs. Connect Pin C5 to Pin C6. Use a separate

trace on the PCB back to a common supply point.

C7 Input VDDA1P1_RF_VCO 1.1 V VCO Supply. Decouple this pin with 1 μF.

C8 Input VDDA1P3_RF_LO

1.3 V LO Generator for the RF Synthesizer. This pin is sensitive to

supply noise.

C10 Input VDDA1P3_AUX_VCO_LDO 1.3 V Supply.

C12 Input VDDA_3P3

General-Purpose Output Pull-Up Voltage and Auxiliary DAC Supply

Voltage.

C14

Input/

output

RBIAS

Bias Resistor. Tie this pin to ground using a 14.3 kΩ resistor. This pin

generates an internal current based on an external 1% resistor.

D10 Input VDDA1P1_AUX_VCO 1.1 V VCO Supply. Decouple this pin with 1 μF.

E4 Input VDDA1P8_BB 1.8 V Supply for the ADC and DAC.

E5 Input VDDA1P3_BB 1.3 V Supply for the ADC, DAC, and AUXADC.

E7, E8 Input

REF_CLK_IN+,

REF_CLK_IN−

Device Clock Differential Input.

E10 Output AUX_SYNTH_OUT Auxiliary PLL Output. When unused, do not connect this pin.

E12 Input VDDA1P8_TX 1.8 V Supply for Transmitter.

F3, F4, F11, E11 Input AUXADC_0 to AUXADC_3

Auxiliary ADC Input. When unused, connect these pins to ground with a

pull-down resistor, or connect directly to ground.

G5 Input VDDA1P3_CLOCK_SYNTH

1.3 V Supply Input for Clock Synthesizer. Use a separate trace on the

PCB back to a common supply point.

G7 Input VDDA1P3_RF_SYNTH 1.3 V RF Synthesizer Supply Input. This pin is sensitive to supply noise.

G8 Input VDDA1P3_AUX_SYNTH 1.3 V Auxiliary Synthesizer Supply Input.

G9 Output RF_SYNTH_VTUNE RF Synthesizer VTUNE Output.

H11

Input/

output

GPIO_12

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

H12

Input/

output

GPIO_11

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

J11

Input/

output

GPIO_13

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

J12

Input/

output

GPIO_10

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be tied

to ground through a resistor (to safeguard against misconfiguration), or it

can be left floating, programmed as output, and driven low.

ADRV9009 Data Sheet

Rev. B | Page 20 of 127

Pin No. Type Mnemonic Description

Input/

output

GPIO_18

Digital GPIO, 1.8 V to 2.5 V. The joint test action group (JTAG) function is

TCLK. Because this pin contains an input stage, the voltage on the pin

must be controlled. When unused, this pin can be tied to ground

through a resistor (to safeguard against misconfiguration), or it can be

left floating, programmed as output, and driven low.

Input/

output

GPIO_2

Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 0.

Because this pin contains an input stage, the voltage on the pin must

be controlled. When unused, this pin can be tied to ground through a

resistor (to safeguard against misconfiguration), or it can be left floating,

programmed as output, and driven low.

Input/

output

GPIO_1

Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 0. Because

this pin contains an input stage, the voltage on the pin must be

controlled. When unused, this pin can be tied to ground through a

resistor (to safeguard against misconfiguration), or it can be left floating,

programmed as output, and driven low.

Input/

output

GPIO_5

Digital GPIO, 1.8 V to 2.5 V. The JTAG function is TDO. Because this pin

contains an input stage, the voltage on the pin must be controlled.

When unused, this pin can be tied to ground through a resistor (to

safeguard against misconfiguration), or it can be left floating,

programmed as output, and driven low.

Input/

output

GPIO_4 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is TRST

. Because this pin

contains an input stage, the voltage on the pin must be controlled.

When unused, this pin can be tied to ground through a resistor (to

safeguard against misconfiguration), or it can be left floating,

programmed as output, and driven low.

Input/

output

GPIO_3

Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 1. Because

this pin contains an input stage, the voltage on the pin must be

controlled. When unused, this pin can be tied to ground through a

resistor (to safeguard against misconfiguration), or it can be left floating,

programmed as output, and driven low.

Input/

output

GPIO_0

Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 1. Because

this pin contains an input stage, the voltage on the pin must be

controlled. When unused, this pin can be tied to ground through a

resistor (to safeguard against misconfiguration), or it can be left floating,

programmed as output, and driven low.

K11

Input/

output

GPIO_14

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

K12

Input/

output

GPIO_9

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

Input/

output

GPIO_6

Digital GPIO, 1.8 V to 2.5 V. The JTAG function is TDI. Because this pin

contains an input stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor (to safeguard

against misconfiguration), or it can be left floating, programmed as

output, and driven low.

Input/

output

GPIO_7

Digital GPIO, 1.8 V to 2.5 V. The JTAG function is TMS. Because this pin

contains an input stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor (to safeguard

against misconfiguration), or it can be left floating, programmed as

output, and driven low.

L11

Input/

output

GPIO_15

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

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