ARM Cortex-M3 技术入门与ST架构解析

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"Cortex-M3入门资料，包含CoreSight Design Kit技术参考手册，版权归属于ARM Limited，仅供学习参考，未经允许不得复制或用于商业用途。文档内容涉及产品的持续发展和改进，所有产品细节和使用说明均以善意提供，但不提供任何明示或暗示的保证，包括但不限于适销性或特定用途的适用性保证。" Cortex-M3是ARM公司设计的一种高效能、低功耗的微控制器内核，广泛应用于嵌入式系统设计。它是ARM Cortex系列的一部分，主要针对实时操作系统（RTOS）和嵌入式应用市场。Cortex-M3基于Thumb-2指令集，该指令集是ARM的16/32位混合指令集，它在保持代码密度的同时提供了更好的性能。 CoreSight Design Kit技术参考手册是理解Cortex-M3处理器架构的关键资源，它详细介绍了CoreSight调试和 trace 技术。CoreSight是ARM开发的一套系统级调试和追踪解决方案，旨在帮助开发者在复杂的嵌入式系统中进行高效调试和性能分析。手册通常会涵盖以下几个方面： 1. **处理器架构**：包括Cortex-M3的处理单元、寄存器结构、中断处理机制以及内存管理单元（MMU）等关键组件的详细信息。 2. **调试接口**：如JTAG和SWD（Serial Wire Debug）接口的使用，这些接口允许开发者通过外部工具连接到Cortex-M3核心进行程序调试。 3. **Trace功能**：CoreSight的Trace功能可以记录处理器执行的详细信息，这对于优化代码性能、理解和分析系统行为至关重要。 4. **开发工具支持**：手册通常会提供如何配合IDE（集成开发环境）、编译器和仿真器进行开发的指导。 5. **系统集成**：介绍如何将Cortex-M3内核集成到SoC（System on Chip）设计中，以及与外设和其他处理器的交互。 6. **知识产权保护**：由于文档涉及到ARM的知识产权，因此文档明确指出未经许可，不得复制或用于商业目的。在学习Cortex-M3时，开发者需要理解其内存模型、中断处理流程、异常处理、中断向量表以及如何编写高效的 Thumb-2 指令代码。同时，熟悉CoreSight调试和追踪工具的使用也是必不可少的技能，这有助于提升开发效率和软件质量。对于初学者来说，这份资料提供了一个深入理解Cortex-M3架构和技术的良好起点。

Debug Access Port

Beta

1.1.1 Structure

The SWJ-DP consists of a wrapper around the JTAG-DP and SW-DP. Its function is to

select JTAG or SWD as the connection mechanism and enable either JTAG-DP or

SW-DP as the interface to the DAP.

1.1.2 Operation

SWJ-DP enables an Application Specific Integrated Circuit (ASIC) to be designed

which can be used in systems that require either a JTAG interface or a SWD interface.

There is a trade-off between the number of pins used and compatibility with existing

hardware and test equipment. There are several scenarios where the use of a JTAG

debug interface must be maintained:

• to enable inclusion in an existing scan chain, generally on-chip TAPs used for test

or other purposes.

• to enable the device to be cascaded with legacy devices which use JTAG for debug

• to enable use of existing debug hardware with the corresponding test TAPs, for

example, in Automatic Test Equipment (ATE).

An ASIC fitted with SWJ-DP support can be connected to legacy JTAG equipment

without any requirement to make changes. If a SWD tool is available, only two pins are

required, instead of the usual four used for JTAG. Two pins are therefore released for

alternative use.

These two pins can only be used when there is no conflict with their use in JTAG mode.

In addition, to support use of SWJ-DP in a scan chain with other JTAG devices, the

default state after reset must be to use these pins for their JTAG function. If the direction

of the alternative function is compatible with being driven by a JTAG debug device, the

transition to a shift state can be used to transition from the alternative function to JTAG

mode.

The alternate function cannot be used while the ASIC is being used in JTAG debug

mode.

The switching scheme is arranged so that, provided there is no conflict on the TDI and

TDO pins, a JTAG debugger is able to connect by sending a specific sequence.

The connection sequence used for SWD is safe when applied to the JTAG interface,

even if hot-plugged, enabling the debugger to continually retry its access sequence. A

sequence with

TMS=1

ensures that JTAG-DP, SW-DP, and the watcher circuit are in a

known reset state. The pattern used to select SWD has no effect on JTAG targets.

SWJ-DP is compatible with a free-running TCK, or a gated clock which is supplied by

the external tools.

Debug Access Port

Beta

1.1.3 JTAG and SWD interface

The external JTAG interface has four mandatory pins, TCK, TMS, TDI, and TDO, and

an optional reset, nTRST. JTAG-DP and SW-DP also require a separate power-on reset,

nPOTRST.

The external SWD interface requires two pins:

• a bidirectional SWDIO signal

• a clock, which can be input or output from the device.

The block level interface has two pins for data plus an output enable, which must be

used to drive a bidirectional pad for the external interface, and clock and reset signals.

To enable sharing of the connector for either JTAG or SWD, connections must be made

external to the SWJ-DP block, as shown in Figure 1-1 on page 1-2. In particular, TMS

must be a bidirectional pin to support the bidirectional SWDIO pin in SWD mode.

When SWD mode is being used, the TDO pin is expected to be re-used for Serial Wire

Output (SWO). The TDI pin is available for use as an alternative input function.

Note

If SWO functionality is required in JTAG mode, a dedicated pin is required.

1.1.4 Clock and reset control interface

In the DBGCLK clock domain, there are registers to enable power control for the

on-chip debug infrastructure. This enables the majority of the debug logic, such as ETM

and ETB, to be powered down by default, and only the serial engine has to be clocked.

A debug session then starts by powering up the remainder of the debug components. In

SWJ-DP, either JTAG-DP or SW-DP can make power-up or reset requests but only if

they are the selected device. Even in a system which does not provide a clock and reset

control interface to the DAP, it is necessary to connect these signals so it appears that a

clock and reset controller is present. This permits correct handshaking of the request

and acknowledge signals to be performed.

1.1.5 SWD and JTAG select mechanism

SWJ-DP enables either a SWD or JTAG protocol to be used on the debug port. To do

this, it implements a watcher circuit that detects a specific 16-bit select sequence on the

DBGTMS pin:

• one 16-bit sequence is used to switch from JTAG to SWD operation

• a different 16-bit sequence is used to switch from SWD to JTAG.

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