AX58100 EtherCAT Slave Controller Datasheet: Features and Specifications

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AX58100是一款专为EtherCAT从站设计的全功能控制器，由ASIX Electronics Corporation制造，于2021年6月30日发布。这款产品具有显著的特点，包括： 1. ** EtherCAT从站控制器 (ESC)**：AX58100作为一款2/3端口EtherCAT从站控制器，支持标准的EtherCAT通信协议，能够高效地与EtherCAT主站进行交互，确保工业自动化网络中的实时性和同步。 2. ** 内置以太网物理层 (PHY)**：它集成有两个兼容IEEE 802.3/802.3u标准的100BASE-TX/100BASE-FX Fast Ethernet PHY，支持全双工通信，并具备PHY环回模式，可实现自检和自动交叉检测（HP Auto-MDI-X），以及自动极性校正。 3. ** 网络配置灵活性**：第三个以太网MIIO端口使得网络配置更加灵活，支持不同的EtherCAT网络架构。 4. ** 大量内存资源**：拥有8个Fieldbus Memory Management Units (FMMUs) 和8个Sync Managers，有助于管理和协调数据传输，同时配备9K字节的RAM，保证了数据处理的高效和稳定性。 5. ** I/O接口**：提供多达32个数字/通用目的输入/输出（GPIO），每个IO可以单独配置，并直接映射到FMMU，提供了强大的I/O扩展能力。 6. ** 串行外设接口 (SPI)**：支持SPI slave接口，采用模式3和MSB优先的数据传输方式，适用于与外部设备通信。 7. ** 本地总线接口**：具备8位或16位数据总线宽度，支持异步通信，同时也支持带有16位数据总线宽度的BHE（Bus Hold Enable）功能，增强数据传输的效率。 8. ** 内存镜像**：支持功能寄存器和ESC寄存器的镜像，便于系统调试和维护。 9. ** 网络配置的兼容性**：AX58100旨在无缝融入各种工业自动化应用环境，满足严格的工业网络需求。 AX58100是一款功能强大、灵活性高的 EtherCAT从站控制器，特别适合在对实时性、通信速度和扩展性有高要求的工业自动化场景中使用，如自动化生产线、机器人控制和智能设备等。它的多种接口和特性使得它成为构建高效、可靠的工业网络的理想选择。

AX58100

EtherCAT Slave Controller

1.4.4 ESC PDI / Function Local Bus Interface

Pin Name

Type

Pin No

Pin Description

LECSn

Local bus ESC Chip Select

LFCSn

Local bus Function Chip Select

LRDn

Local bus Read

LWRn

Local bus Write

LBHE

Local bus Byte High Enable (16-bit width only)

LRDY

O5/T

Local bus Ready

LINT

O5/T

Local bus Interrupt

LA[13:0]

66, 42, 52,

50, 48, 44,

17, 14, 12, 9,

7, 49, 74, 71

Local bus Address bus

LDA[15:8]

18, 15, 13,

11, 8, 76, 75,

Local bus Data bus [15:8]

LDA[7:0]

69, 67, 53,

60, 51, 4, 47,

Local bus Data bus [7:0]

Note: “Function” means the design for PWM, Incremental/Hall Encoder, SPI Master, I/O Watchdog and Bridge

function, excluding ESC.

Table 1-6: PDI Local Bus Interface Pin Description

1.4.5 PWM Motor Controller

Pin Name

Type

Pin No

Pin Description

PWM1L

O5/T

PWM 1 Low pin or STEP pin

PWM1H

O5/T

PWM 1 High pin or DIR pin

PWM2L

O5/T

PWM 2 Low pin

PWM2H

O5/T

PWM 2 High pin

PWM3L

O5/T

PWM 3 Low pin

PWM3H

O5/T

PWM 3 High pin

PULA

Pulse A, programmable point A

PULB

Pulse B, programmable point B

PULZ

Pulse Z, PWM period start point

PULC

Pulse C, PWM period central point

PULAB

Pulse AB, toggle when programmable point A and B

EMn

Emergency input, active low

Table 1-7: PWM Motor Controller Pin Description

1.4.6 Incremental / Hall Encoder Interface

Pin Name

Type

Pin No

Pin Description

ENCA

ENC input A, Sin., CW, CLK, or HALL A

ENCB

ENC input B, Cos., CCW, DIR, or HALL B

ENCZ

ENC input Z, Zero point or HALL C

Table 1-8: Incremental/Hall Encoder Interface Pin Description

AX58100

EtherCAT Slave Controller

2 Function Description

Clocks/Resets

The AX58100 requires a crystal (25MHz, ±25 PPM at room temperature) as the clock source. Internal PLL

generates the 100MHz clock for EtherCAT Slave Controller (ESC) and also for other functions.

The AX58100 has three reset sources. First, during the VCCK power-on, the internal Power-On-Reset (POR) can

generate a reset pulse to reset all the function blocks when the VCCK power pin rises to a certain threshold voltage

level. The second reset is RSTn pin, which is to do the fundamental reset. And third, EtherCAT command reset,

the EtherCAT master can send reset sequence to force AX58100 reset. AX58100 also supports a reset output

RSTO polarity bootstrap configuration (RSTO_POL).

EtherCAT Slave Controller (ESC)

The AX58100 implements a 3-port EtherCAT slave controller (ESC), licensed from Beckhoff Automation, with

9 Kbytes Process Data RAM, 8 Fieldbus Memory Management Units (FMMUs), 8 Sync-Managers and a 64-bit

Distributed Clock.

Port 0 and 1 integrate embedded Ethernet PHYs, and port 2 is an optional MII interface which are multi-function

pins shared with other interfaces (i.e. PWM, Hall, Local Bus, Digital I/O). Packets are forwarded in the following

order: Port 0->EtherCAT Processing Unit->Port 1->Port 2.

The Process Data Interface (PDI, also named host interface) provides SPI slave, asynchronous 8/16-bit

microcontroller interface (also named Asynchronous Local Bus) and Digital I/O. The SPI slave and asynchronous

8/16-bit Local Bus interface will be used when external MCU in employed the slave system, and the Digital I/O

is used for when direct I/O control.

The AX58100 supports function register mirror from/to ESC memory space. The mirror registers located at process

data memory address from 0x3000 to 0x33FF.

For detailed information about the EtherCAT technology, the EtherCAT core mechanisms, and major features, we

refer to the official standard documentations and guidelines available from ETG (www.ethercat.org, ETG.1000),

IEC (http://www.iec.ch, IEC61158, IEC61784-2, IEC 61800-7), and Beckhoff (http://www.beckhoff.de, technical

specification) web sites.

Ethernet PHY

The AX58100 is embedded two DSP-based Ethernet PHYs, which are fully compliant with the 100BASE-TX and

100BASE-FX Ethernet standards such as IEEE 802.3u, and ANSI X3.263-1995 (FDDI-TP-PMD). In copper

mode, it supports the MDI/MDIX auto-crossover function (HP Auto-MDIX).

Bridge Function

The AX58100 has two memory spaces, one for ESC and another for AX58100 specific functions. The bridge

handles data synchronization between ESC’s memory and function registers, and uses EthterCAT packet’s SOF,

EOF, ESC control signal: SYNCx and LATx, PDI chip select (ESC and function) asserts and de-assert, the PWM

cycle starts, register writes and register data change, total 13 sources to synchronize two space’s register content.

Each function mirror could be enabled independent, the interrupt related registers mirror (INTCR and INTSR) are

also enabled when any function mirror is enabled.

AX58100

EtherCAT Slave Controller

I/O Watchdog

The I/O Watchdog is for AX58100 safety engine and used to monitor I/O signals toggle status and an emergency

stop input (EMn) pin. When I/O signals don't match a pattern or keep over excepted time, the watchdog will be

triggered, or EMn input pin asserted which would force I/O pads to enter default level. The default level is

configurable which could be driven low, high or Tristate.

PWM Controller

The PWM control module provides Pulse Width Modulation (PWM) and STEP / DIR to control motor driving.

The PWM mode has eight pins. There are three pairs of control signal. Each control signal pair has a high pulse

pin (PWMxH) and low pulse pin (PWMxL) control power drive circuit. Others are two alignment pins, PULZ and

PULC point cycle start and central time, and three programmable trigger pins, PULA PULB and PULAB. The

step pulse mode has 2 pins, step (STEP) and direction (DIR), which connect to step motor controller and share

PWM1H/L pins.

The PWM supports up to 12.5MHz output frequency, and programmable polarity, timing adjustment.

Incremental and Hall Encoder Interface

The AX58100 provides an interface with a linear or rotary incremental encoder to get position information, and

supports four input modes, including the Sin/Cos mode (A / B / Z pins), Clock-Wise mode (CW / CCW / Z pins),

Direction-Clock mode (DIR / CLK / Z pins) and the Hall mode (A / B / C pins). It can accumulate positions in

three modes, Sin/Cos, Clock-Wise and Direction-Clock modes, and calculate the GAP time in Hall mode.

The Sin/Cos mode supports input frequency up to 8.33MHz, CW/CCW and DIR/CLK up to 16.66MHz, and the

Hall mode up to 2.77MHz respectively.

SPI Master Controller

The Serial Peripheral Interface (SPI) master controller provides a full-duplex, synchronous serial communication

interface (4 wires) to flexibly work with numerous SPI peripheral devices or microcontroller with the SPI slave.

The SPI master controller supports 4 types of interface timing modes, namely, mode 0, 1, 2, and 3 to allow working

with most SPI devices available. It also supports MSB/LSB first data transfer.

The SPI master controller supports 8 channels, which could sequentially access per device, and supports variable

transfer length up to 8 bytes each channel. It also supports multi-channel access to the same device, and the data

length could be up to 64bytes. For high performance applications, the SPI master controller supports continuous

transfer data between the SPI device and data registers.

The SPI master controller provides 4 chip select, supports one-cold encode output (up to 4 devices), or uses binary

encode output (use an external binary decoder) up to 8 devices.

The SPI master controller supports standard SPI device access without glue logic circuit. Besides, it supports

“trigger data ready input” for ADC application, and also supports “data loaded indication out” and “data path daisy

chain” for DAC application.

The MSCLK (SPI clock) is programmable by software and can run up to 50MHz.

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马海峰

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