提升电源纹波抑制的电流模式带隙基准电路设计与分析

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本文是一篇深入研究的"具有高电源纹波抑制比的电流模式带隙基准的分析与设计"的研究论文，发表在《微电子学杂志》(Microelectronics Journal)上，该期刊的网址为www.elsevier.com/locate/mejo。作者团队由来自中国南方科技大学、南开大学和韩国首尔索格朗大学的学者组成，他们在文章中探讨了电流模式带隙参考电路(Bandgap Reference, BGR)的设计优化策略。传统上，电流模式BGR电路依赖于频率补偿来确保其在宽范围电源电压波动下的稳定性。然而，本文的重点在于通过引入改进的频率补偿方法，显著提升了电路的电源纹波抑制比（Power Supply Rejection Ratio, PSRR）。PSRR是衡量一个电路对电源电压波动反应能力的重要指标，它直接影响到电路的精度和可靠性。文章的核心内容包括： 1. **电流镜 cascode 结构**：利用 cascode 电流镜技术，这种结构可以有效地控制电流，提高电路的线性度和带宽，从而增强 PSRR。 2. **频率补偿的创新**：作者对传统频率补偿方案进行了微调，可能是通过改变反馈路径、调整元件参数或者采用新型拓扑结构，以实现更有效的抑制电源纹波的效果。 3. **实验结果与分析**：文中详细展示了改进后的BGR电路在不同电源条件下的 PSRR 测试结果，以及与传统设计的比较，以证明其优越性能。 4. **稳定性考虑**：除了 PSRR，电路的稳定性也是一个关键因素。论文可能讨论了如何在增强 PSRR 的同时，保持电路的动态稳定性和温度漂移在可接受范围内。 5. **潜在应用和前景**：最后，作者可能会对未来可能的应用领域、设计挑战以及进一步提升 PSRR 的可能性进行探讨，以推动该领域的研究发展。这篇论文不仅提供了关于电流模式带隙基准电路设计的实用改进方法，还为提高电源纹波抑制比提供了一种新的设计思路，对于追求高性能、低噪声电子系统的工程师来说，具有重要的参考价值。

Contents lists available at ScienceDirect

Microelectronics Journal

journal homepage: www.elsevier.com/locate/mejo

Analysis and design of a current-mode bandgap reference with high power

supply ripple rejection

Lidan Wang

a,b

, Chenchang Zhan

⁎

, Junyao Tang

, Shuangxing Zhao

, Guigang Cai

, Yang Liu

Qiwei Huang

a,c

, Guofeng Li

Department of Electrical and Electronic Engineering, Southern University of Science and Technology, Shenzhen, China

College of Electronic Information and Optical Engineering, Nankai University, Tianjin, China

Department of Electronics Engineering, Sogang University, Seoul, Korea

ARTICLE INFO

Keywords:

Bandgap reference

Current-mode

Cascode current mirror

Frequency compensation

Power supply ripple rejection

Stability

ABSTRACT

In this paper, a current-mode bandgap reference (BGR) circuit with cascode current mirrors and improved

frequency compensation for achieving high power supply ripple rejection (PSRR) is presented. By slightly

modifying a conventional frequency compensation scheme, the PSRR of the BGR is signiﬁcantly enhanced.

PSRRs of the BGR with the two diﬀerent compensation techniques have been formulated and veriﬁed. Moreover,

design considerations are presented, taking into account the critical parasitic capacitor's eﬀect in PSRR. To our

knowledge, this is the ﬁrst time in the literature of explicitly demonstrating how the PSRR of a BGR is improved

due to the frequency compensation. The feedback loop stability is also analyzed. The measured PSRR of an

example BGR using the modiﬁed compensation fabricated in a standard 0.18-μm CMOS process is −77 dB and

−62 dB at 1 kHz, and 100 kHz, respectively, with more than 40 dB improvement at the high frequency ranges

over the design with the classical compensation.

1. Introduction

Reference voltage generators are critical components in analog,

mixed-signal, power management and radio-frequency circuits and

systems. The generators are required to be stabilized over process,

voltage and temperature variations, and also to be implemented

without modiﬁcation of fabrication process. The bandgap reference

(BGR) is one of the most popular reference voltage generators that

successfully achieve the requirements [1]. In order to generate a stable

reference voltage for high precision applications, it is necessary that the

reference circuit should have high power supply rejection ratio (PSRR)

[2,3]. Many solutions exist in literature for improving the PSRR

[4–8,13–18]. But the power consumption is very high and the circuit

structure is rather complicated. Therefore, a simple method with im-

proved frequency compensation techniques is adopted to maximize the

PSRR in this work. For the rest part of this paper, the design con-

siderations of a high-PSRR current-mode BGR with an emphasis on

PSRR and stability analysis are described in Sections 2 and 3; the

measured results of an example design in a 0.18-μm CMOS process are

presented in Section 4, and some concluding remarks are given in

Section 5.

2. PSRR analysis of BGR

2.1. PSRR analysis of the conventional BGR

To reduce the supply voltage requirement, a BGR that employs a

weighted sum of a proportional-to-absolute-temperature (PTAT) and

complementary-to-absolute-temperature (CTAT) current to produce the

low-tempco (temperature coeﬃcient, or TC) reference voltage was de-

veloped in [1]. Without sacriﬁcing the voltage headroom too much, a

low-voltage cascode current mirror can be adopted to improve the loop

gain and line sensitivity or the low-frequency PSRR. Hence, it is not

diﬃcult to arrive at a current-mode BGR with cascode current mirror,

as shown in Fig. 1, whereby the conventional dominant pole based

frequency compensation is assumed [2]. The error ampliﬁer used in the

BGR is shown in Fig. 2. Self-bias technology is used to reduce the power

supply sensitivity of the ampliﬁer, and the bias current IB is derived

from the bandgap core shown in Fig. 1. The startup circuit is used to

prevent the BGR from staying at the undesired zero operating point.

The cascode current mirrors are used in the ampliﬁer to increase the

output resistance and hence the loop gain. Since the output resistance at

node C is much larger than node A and node B, the dominant pole

http://dx.doi.org/10.1016/j.mejo.2017.08.011

Received 16 December 2016; Received in revised form 25 April 2017; Accepted 24 August 2017

⁎

Corresponding author at: Department of Electrical and Electronic Engineering, Southern University of Science and Technology, Shenzhen, China.

E-mail addresses: wangld@sustc.edu.cn (L. Wang), zhancc@sustc.edu.cn (C. Zhan), tanjy3@mail.sustc.edu.cn (J. Tang), zhaosx@mail.sustc.edu.cn (S. Zhao),

caigg@mail.sustc.edu.cn (G. Cai), liuy8@mail.sustc.edu.cn (Y. Liu), huangqw@sustc.edu.cn (Q. Huang), ligf@nankai.edu.cn (G. Li).

Microelectronics Journal 68 (2017) 7–13

MARK

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