LM98714: 三通道16位45MSPS模拟前端带LVDS/CMOS输出和集成CCD/CISS传感器时钟发生器

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"TI-LM98714是一款三通道、16位、45MHz采样率的模拟前端，带有LVDS/CMOS输出和集成的CCD/CISS传感器时序发生器的集成电路。" TI公司的LM98714是一款专为高性能成像应用设计的模拟前端集成电路。这款芯片提供了LVDS（低压差分信号）和CMOS两种输出模式，能够适应不同的系统需求。其核心功能之一是作为CCD（电荷耦合器件）或CISS（互补金属氧化物半导体传感器）的时序发生器，能够灵活地控制这些传感器的工作时序。 LM98714具有独立的增益/偏置校正功能，允许每个通道进行单独调整，以优化图像质量。此外，每个通道还配备有数字黑电平校正环路，可以消除图像中的暗电流噪声。该芯片的另一个显著特点是可编程输入钳位电压，可以根据不同的传感器特性和环境条件进行定制。集成的CCD/CISS传感器时序发生器提供了一种灵活的方式来控制传感器的读出速度和同步信号，确保数据准确无误地传输到后续的图像处理器或ASIC（应用特定集成电路）。此特性使得LM98714适用于各种高分辨率、高速度的成像应用。在性能规格方面，LM98714的最大输入电平可在1.2伏或2.4伏模式下工作，支持正负极性选项。其ADC（模数转换器）分辨率为16位，采样率高达45兆样本每秒（MSPS），具有较高的数据采集效率。线性度（INL，积分非线性）典型值为±23 LSB，确保了良好的信号转换精度。每个通道的采样特性保证了高质量的图像数据输出。 TI的LM98714是一款针对高精度、高速度成像应用设计的模拟前端解决方案，集成了关键的信号处理功能，如时序控制、增益和偏置校正，以及数字黑电平校正，能够满足各种复杂成像系统的需求。结合SPI（串行外围接口）和其他电机控制器，可以构建一个完整的图像采集和处理系统。用户可以通过TI提供的技术文档、工具和软件，以及社区支持，来充分利用这个器件的功能并进行系统级设计。

CLAMP

SAMPLE

HOLD

PAR

PIXEL

VCLP

LM98714

SNAS254B –OCTOBER 2006–REVISED APRIL 2017

www.ti.com

Product Folder Links: LM98714

To provide a more precise DC bias point (i.e. a voltage closer to the Black Level voltage), the CLPIN pulse can

be “gated” by the internally generated SAMPLE clock. This resulting CLPIN

GATED

signal is the logical “AND” of

the SAMPLE and CLPIN signals as shown in Figure 3. By using the CLPIN

GATED

signal, the higher Reset Noise

peak will not be included in the clamping period and only the average of the Reset Level and Black Level

components of the CCD waveform will be centered around VCLP.

Figure 5. Equivalent Input Switched Capacitance S/H Mode

In Sample and Hold Mode, the impedance of the analog input pins is dominated by the switched capacitance of

the CDS/Sample and Hold amplifier. The amplifier switched capacitance, shown as C

in Figure 4, and internal

parasitic capacitances can be estimated by a single capacitor switched between the analog input and the VCLP

reference pin for Sample and Hold mode. During each pixel cycle, the modeled capacitor, C

, is charged to the

-VCLP voltage then discharged. The average input current at the OS

pin can be calculated knowing the

input signal amplitude and the frequency of the pixel. If the application requires AC coupling of the CCD output to

the LM98714 analog inputs, the Sample and Hold Mode input bias current may degrade the DC bias point of the

coupling capacitor. To overcome this, Input Source Follower Buffers are available to isolate the larger Sample

and Hold Mode input bias currents from the analog input pin (as discussed in the following section). As shown in

Figure 6, the input bias current is much lower for CDS mode, eliminating the need for the source follower buffers.

7.3.3.1 CDS Mode

Figure 6. CDS Mode Simplified Input Diagram

Correlated Double Sampling mode does not require as precise a DC bias point as does Sample and Hold mode.

This is due mainly to the nature of CDS itself, that is, the Video Signal voltage is referenced to the Reset Level

voltage instead of the static DC VCLP voltage. The common mode voltage of these two points on the CCD

waveform have little bearing on the resulting differential result. However, the DC bias point does need to be

established to ensure the CCD waveform’s common mode voltage is within rated operating ranges.

The CDS mode biasing can be performed in the same way as described in the Sample/Hold Mode Biasing

section, or, an alternative method is available which precludes the need for a CLPIN pulse. Internal resistor

dividers can be switched in across the OS

, OS

, and/or OS

inputs to provide the DC bias voltage.

CLAMP

SAMPLE

HOLD

PAR

BIAS

LM98714

www.ti.com

SNAS254B –OCTOBER 2006–REVISED APRIL 2017

Product Folder Links: LM98714

Figure 7. CDS Mode Input Bias Current

Unlike in Sample and Hold Mode, the input bias current in CDS Mode is relatively small. Due to the architecture

of CDS switching, the average charge loss or gain on the input node is ideally zero over the duration of a pixel.

This results in a much lower input bias current, whose main source is parasitic impedances and leakage

currents. As a result of the lower input bias current in CDS Mode, maintaining the DC Bias point the input node

over the length of a line will require a much smaller AC input coupling capacitor.

7.3.3.2 Input Source Follower Buffers

The OS

, OS

inputs each have an optional Source Follower Buffer which can be selected with Main

Configuration Register 1, Bit[7]. These source followers provide a much higher impedance seen at the inputs. In

some configurations, such as Sample and Hold Mode with AC coupled inputs, the DC bias point of the input

nodes must remain as constant as possible over the entire length of the line to ensure a uniform comparison to

reference level (VCLP in this case). The Source Followers effectively isolate the AC input coupling capacitor from

the switched capacitor network internal to the LM98714’s Sample and Hold/CDS Amplifier. This results in a

greatly reduced charge loss or gain on the AC Input coupling capacitor over the length of a line, thereby

preserving its DC bias point.

The Source Followers should only be used in the 1.2 V input range (i.e. Main Configuration Register 2, Bit[4] = 1,

CDS Gain = 2x). Using the Source Followers in the 2.4 V (i.e. Main Configuration Register 2, Bit[4] = 0, CDS

Gain = 1x). input range will result in a loss of performance (mainly linearity performance at the high and low ends

of the input range).

7.3.3.3 VCLP DAC

The VCLP pin provides the reference level for incoming signals in Sample and Hold Mode. The pin’s voltage can

be set by one of three sources by writing to the VCLP Configuration Register on register page 0. By default, the

VCLP pin voltage is established by an internal resistor divider which sets the voltage to VA/2. The resistor ladder

can be disconnected and the pin driven externally by the application.

The most flexible method of setting the VCLP voltage is using the internal VCLP DAC buffer. The DAC is

connected by setting the VCLP Configuration register Bit[5:4] to 2b’01. The DAC has a four bit “offset binary”

format which is summarized in Table 2. The DAC output has an approximate swing of ±1.2 V.

Table 2. VCLP DAC Format

VCLP Configuration [3:0] Typical VCLP Output

0 -Full Scale

0111 Mid Scale - LSB

1000 Mid Scale

1001 Mid Scale + 1 LSB

1111 +Full Scale

INCLK (Pixel Rate)

φ1A output from LM98714

CCD Timing generator

φ1A input at CCD

(after inverter)

Pixel output from CCD

The LM98714 internal clock tree creates a small amount of

delay in the CCD Timing generator outputs.

Application board discrete logic also creates propagation delay

with respect to the input clock.

Finally, the CCD propagation delay further shifts the Pixel

signal input to the LM98714 from the input clock.

PIXPHASE0

(default “coarse’ pixel phase)

CLAMP

(internal pixel reference

level sampling clock)

SAMPLE

(internal pixel data level

sampling clock)

Default CLAMP fine

adjust window

Default CLAMP fine

adjust window

Default SAMPLE

fine adjust window

Maximum fine adjust

not good enough for

default PIXPHASE,

CLAMP and SAMPLE

are too early due to

propagation delays.

LM98714

SNAS254B –OCTOBER 2006–REVISED APRIL 2017

www.ti.com

Product Folder Links: LM98714

In a real system however, propagation delays exist in all stages of the signal chain. These propagation delays

will lead to a shift in the CCD Pixel outputs with respect to the LM98714 input clock. The phase shift of the CCD

Pixel output, demonstrated in Figure 10, can lead to significant sample timing issues if not properly corrected.

Figure 10. CCD Output Phase Shift in a Real Application

In the default mode, the LM98714 sampling is performed during a clock period whose phase is aligned with the

input clock (ignoring any clock tree skew for the moment). The actual sampling clocks are adjustable within the

clock period, as shown in Figure 10 (shown for CDS mode in the diagram) and further described in the Internal

Sample Timing section. As shown in the diagram, the delay of the CCD Pixel output is shifted far enough that the

fine CLAMP and SAMPLE clocks cannot be placed in a stable portion of the waveform. To remedy this situation,

the LM98714’s Coarse Pixel Phase Alignment feature allows the designer to shift the entire phase of the analog

front end with respect to the input clock. This allows the designer to choose one of four sampling phases which

best matches the delay in the external circuitry. Once the “Coarse Pixel Phase ” has been chosen, the designer

can then fine tune the sampling clocks using the fine adjustment (see Internal Sample Timing).

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