NVM-Express 1.2规范发布：2014年11月更新

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"NVM-Express 1.2 是一种高速、低延迟的存储接口标准，用于连接非易失性内存（Non-Volatile Memory, NVMe）设备，如固态硬盘（SSD）到计算机的主机控制器。这个规范是在2014年11月3日发布的第1.2版，标志着对NVMe技术的重要进展，它旨在提高数据传输速度和系统性能。 NVMExpress 1.2 修订版提供了对新技术的标准化支持，包括但不限于更高的带宽、更低的延迟以及更优化的数据传输路径，使得NVMe SSD在存储系统中的性能表现大幅提升。它采用了一种基于PCIe（Peripheral Component Interconnect Express）的总线架构，允许NVMe设备直接与CPU进行通信，跳过了传统的硬盘控制器，从而实现了更快的数据访问。该规范的下载链接位于NVMExpress官网（http://nvmexpress.org），并且声明所有内容受NVMExpress, Inc.的版权保护。对于NVMExpress成员，他们有权在遵守组织的知识产权政策、会员协议及法律条款的前提下使用和实施此规格。非成员获取此文档只能用于查看或引用，且必须承认NVMExpress的版权。 NVMExpress 1.2 的发布对于推动NVMe技术的普及和数据中心优化具有重要意义，因为它允许硬件厂商开发出更高效、更符合现代计算需求的存储解决方案。随着其广泛应用，我们见证了云计算、大数据分析和高性能计算等领域中存储性能的显著提升，进一步加速了现代信息技术的发展。"

NVM Express 1.2

1.6.17 namespace

A quantity of non-volatile memory that may be formatted into logical blocks. When formatted, a

namespace of size n is a collection of logical blocks with logical block addresses from 0 to (n-1).

1.6.18 Namespace ID

An identifier used by a controller to provide access to a namespace. The NSID value of FFFFFFFFh is

used to indicate all namespaces. An invalid namespace ID is a namespace ID whose value is zero or

whose value is greater than the value reported by the Number of Namespaces (NN) field in the Identify

Controller data structure. All other namespace IDs are valid. A valid namespace ID that maps to an

attached namespace is an active namespace ID. A namespace shall be attached to a controller before

host software may submit I/O commands for that namespace. A valid namespace ID that does not map

to an attached namespace is an inactive namespace ID. A valid namespace ID becomes inactive when

the associated namespace is detached or deleted.

If Namespace Management is supported then Namespace IDs shall be unique within the NVM subsystem

(e.g., namespace ID of 3 shall refer to the same physical namespace regardless of the accessing

controller). If Namespace Management is not supported then Namespace IDs for private namespaces are

not required to be unique.

1.6.19 NVM

NVM is an acronym for non-volatile memory.

1.6.20 NVM subsystem

An NVM subsystem includes one or more controllers, one or more namespaces, one or more PCI

Express ports, a non-volatile memory storage medium, and an interface between the controller(s) and

non-volatile memory storage medium.

1.6.21 private namespace

A namespace that is accessible by only one controller. A host may determine whether a namespace is a

private namespace or may be a shared namespace by the value of the Namespace Multi-path I/O and

Namespace Sharing Capabilities (NMIC) field in the Identify Namespace data structure.

1.6.22 Runtime D3 (Power Removed)

In Runtime D3 (RTD3) main power is removed from the controller. Auxiliary power may or may not be

provided.

1.6.23 shared namespace

A namespace that is accessible by two or more controllers in an NVM subsystem. A host may determine

whether a namespace is a private namespace or may be a shared namespace by the value of the

Namespace Multi-path I/O and Namespace Sharing Capabilities (NMIC) field in the Identify Namespace

data structure.

1.7 Keywords

Several keywords are used to differentiate between different levels of requirements.

1.7.1 mandatory

A keyword indicating items to be implemented as defined by this specification.

1.7.2 may

A keyword that indicates flexibility of choice with no implied preference.

NVM Express 1.2

2 System Bus (PCI Express) Registers

This section describes the PCI Express register values when the PCI Express is the system bus used.

Other system buses may be used in an implementation. If a system bus is used that is not a derivative of

PCI, then this section is not applicable.

This section details how the PCI Header, PCI Capabilities, and PCI Express Extended Capabilities should

be constructed for an NVM Express controller. The fields shown are duplicated from the appropriate PCI

or PCI Express specifications. The PCI documents are the normative specifications for these registers

and this section details additional requirements for an NVM Express controller.

Start

End

Name

Type

00h

3Fh

PCI Header

PMCAP

PMCAP+7h

PCI Power Management Capability

PCI Capability

MSICAP

MSICAP+9h

Message Signaled Interrupt Capability

PCI Capability

MSIXCAP

MSIXCAP+Bh

MSI-X Capability

PCI Capability

PXCAP

PXCAP+29h

PCI Express Capability

PCI Capability

AERCAP

AERCAP+47h

Advanced Error Reporting Capability

PCI Express Extended Capability

MSI-X is the recommended interrupt mechanism to use. However, some systems do not support MSI-X,

thus devices should support both the MSI Capability and the MSI-X Capability.

It is recommended that implementations support the Advanced Error Reporting Capability to enable more

robust error handling.

2.1 PCI Header

Start

End

Symbol

Name

00h

03h

Identifiers

04h

05h

CMD

Command Register

06h

07h

STS

Device Status

08h

RID

Revision ID

09h

0Bh

Class Codes

0Ch

CLS

Cache Line Size

0Dh

MLT

Master Latency Timer

0Eh

HTYPE

Header Type

0Fh

BIST

Built In Self Test (Optional)

10h

13h

MLBAR

(BAR0)

Memory Register Base Address, lower 32-bits <BAR0>

14h

17h

MUBAR

(BAR1)

Memory Register Base Address, upper 32-bits <BAR1>

18h

1Bh

IDBAR

(BAR2)

Index/Data Pair Register Base Address <BAR2>

(Optional)

1Ch

1Fh

BAR3

Reserved <BAR3>

20h

23h

BAR4

Vendor Specific

24h

27h

BAR5

Vendor Specific

28h

2Bh

CCPTR

CardBus CIS Pointer

2Ch

2Fh

Subsystem Identifiers

30h

33h

EROM

Expansion ROM Base Address (Optional)

34h

CAP

Capabilities Pointer

35h

3Bh

Reserved

3Ch

3Dh

INTR

Interrupt Information

3Eh

MGNT

Minimum Grant (Optional)

3Fh

MLAT

Maximum Latency (Optional)

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庾志辉

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