STM32F103修正手册：嵌入式工程师必备

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"STM32F103勘误手册提供了关于ST Microelectronics STM32F101x8/B, STM32F102x8/B, 和STM32F103x8/B中密度设备的限制信息，以及STM32F102xx USB访问线设备的修订版Y, 1, 2, 和X的错误信息。手册针对这些产品家族的ARM Cortex-M3核心进行了详尽的错误分析。" STM32F103系列微控制器是基于ARM Cortex-M3内核的高性能MCU，广泛应用于嵌入式系统设计。勘误手册是工程师在设计和调试过程中不可或缺的参考资料，它纠正了产品在生产过程中可能存在的硬件或软件问题，确保设备的稳定性和可靠性。该手册的适用范围包括B、Z、Y、1、2、3和X修订版的STM32F101xx访问线产品和STM32F103xx性能线产品，以及Y、1、2和X修订版的STM32F102xx USB访问线设备。这些修订版信息有助于识别不同批次的芯片，以便于追踪和解决潜在的问题。手册中提到的硅片识别方法有两方面：一是通过设备封装下的修订代码，二是通过包装盒标签上最后三位内部订单代码。这为工程师在实际应用中确认器件版本提供了便利。 STM32F10xxx参考手册详细介绍了如何通过DBGMCU_IDCODE寄存器的REV_ID位来确定设备的修订代码。这一功能使得工程师能够快速判断芯片的具体版本，从而知道可能存在的限制和问题。表1列出了设备识别的方法，而表2则展示了完整的根部件编号列表，这对于管理和跟踪不同修订版的设备至关重要。此外，附录A提供了有关设备标记上修订代码识别的详细信息。 STM32F103勘误手册对于嵌入式系统的开发者来说是一个宝贵的工具，它帮助工程师了解和解决STM32F103系列微控制器在实际应用中可能出现的问题，确保产品的质量和性能。通过深入理解和利用此手册，工程师可以更有效地优化其设计，提高产品的稳定性和兼容性。

ARM

32-bit Cortex

-M3 limitations STM32F10xx8 STM32F10xxB

8/41 DocID14574 Rev 13

1.1 Cortex-M3 limitations description for STM32F10xxx medium-

density devices

Only the limitations described below have an impact, even though minor, on the

implementation of STM32F10xxx medium-density devices.

All the other limitations described in the ARM errata notice (and summarized in Table 3

above) have no impact and are not related to the implementation of STM32F10xxx medium-

density devices (Cortex-M3 r1p1-01rel0).

1.1.1 Cortex-M3 LDRD with base in list may result in incorrect base register

when interrupted or faulted

Description

The Cortex-M3 Core has a limitation when executing an LDRD instruction from the system-

bus area, with the base register in a list of the form LDRD Ra, Rb, [Ra, #imm]. The

execution may not complete after loading the first destination register due to an interrupt

before the second loading completes or due to the second loading getting a bus fault.

Workarounds

1. This limitation does not impact the STM32F10xxx code execution when executing from

the embedded Flash memory, which is the standard use of the microcontroller.

2. Use the latest compiler releases. As of today, they no longer generate this particular

sequence. Moreover, a scanning tool is provided to detect this sequence on previous

releases (refer to your preferred compiler provider).

1.1.2 Cortex-M3 event register is not set by interrupts and debug

Description

When interrupts related to a WFE occur before the WFE is executed, the event register

used for WFE wakeup events is not set and the event is missed. Therefore, when the WFE

is executed, the core does not wake up from WFE if no other event or interrupt occur.

Workaround

Use STM32F10xxx external events instead of interrupts to wake up the core from WFE by

configuring an external or internal EXTI line in event mode.

1.1.3 Cortex-M3 BKPT in debug monitor mode can cause DFSR mismatch

Description

A BKPT may be executed in debug monitor mode. This causes the debug monitor handler

to be run. However, the bit 1 in the Debug fault status register (DFSR) at address

0xE000ED30 is not set to indicate that it was originated by a BKPT instruction. This only

occurs if an interrupt other than the debug monitor is already being processed just before

the BKPT is executed.

DocID14574 Rev 13 9/41

STM32F10xx8 STM32F10xxB ARM

32-bit Cortex

-M3 limitations

Workaround

If the DFSR register does not have any bit set when the debug monitor is entered, this

means that we must be in this “corner case” and so, that a BKPT instruction was executed

in debug monitor mode.

1.1.4 Cortex-M3 may freeze for SLEEPONEXIT single instruction ISR

Description

If the Cortex-M3 SLEEPONEXIT functionality is used and the concerned interrupt service

routine (ISR) contains only a single instruction, the core becomes frozen. This freezing may

occur if only one interrupt is active and it is preempted by an interrupt whose handler only

contains a single instruction.

However, any new interrupt that causes a preemption would cause the core to become

unfrozen and behave correctly again.

Workaround

This scenario does not happen in real application systems since all enabled ISRs should at

least contain one instruction. Therefore, if an empty ISR is used, then insert an NOP or any

other instruction before the exit instruction (BX or BLX).

1.1.5 Interrupted loads to SP can cause erroneous behavior

Description

If an interrupt occurs during the data-phase of a single word load to the stack-pointer

(SP/R13), erroneous behavior can occur. In all cases, returning from the interrupt will result

in the load instruction being executed an additional time. For all instructions performing an

update to the base register, the base register will be erroneously updated on each

execution, resulting in the stack-pointer being loaded from an incorrect memory location.

The affected instructions are:

1. LDR SP,[Rn],#imm

2. LDR SP,[Rn,#imm]!

3. LDR SP,[Rn,#imm]

4. LDR SP,[Rn]

5. LDR SP,[Rn,Rm]

Workaround

As of today, there is no compiler generating these particular instructions. This limitation can

only occur with hand-written assembly code.

Both issues may be worked around by replacing the direct load to the stack-pointer, with an

intermediate load to a general-purpose register followed by a move to the stack-pointer.

Example: the following instruction "LDR SP, [R0]" can be replaced by

“LDR R2,[R0]

MOV SP,R2 "

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