I2C总线v2.1详解：设计者与制造商的福音

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I2C (Inter-Integrated Circuit) 是一种在低电压、低数据速率下进行串行通信的接口标准，它最初由Philips Semiconductors（现为NXP Semiconductors）开发，于1982年发布。这份"V2.1 I2C-bus Specification"文档详细阐述了I2C协议的各个方面，旨在帮助设计师和制造商了解并有效利用I2C技术。 1. I2C简介 I2C版本更新历史表明，从最初的1.0版本（1992年）到2.0版本（1983年），再到2.1版本（1999年），不断优化以适应新的需求和技术进步。购买Philips的I2C组件时，确保选择符合最新规范的产品至关重要。 2. I2C的优点对于设计者来说，I2C提供了一系列优点：它简化了系统设计，减少了线路数量，节省空间；支持多个器件共享同一数据线，提高了系统的灵活性；而且由于其简单易用的协议，学习曲线较平缓，有利于快速集成。制造商则可以从I2C的低成本、高效能和标准化特性中受益，这有助于降低生产成本，提升产品的可靠性，并且促进不同供应商设备之间的兼容性。 3. I2C通信概念 I2C的核心是通过两条信号线（SDA和SCL）实现双向通信。SDA用于数据传输，SCL控制数据的传输节奏。该协议支持两种模式：标准模式和快速模式，还有高级的高速模式（Hs-Mode）和高容量模式（HSB-Mode），以适应不同的应用需求。 4. 数据传输与位交换数据以字节形式传输，每个字节都有明确的格式。传输开始于一个START条件，结束于STOP条件。数据有效性检查（ACKnowledge）在接收端进行，确保数据的正确接收。 5. 仲裁与同步在多主设备连接的系统中，I2C使用仲裁机制来解决数据冲突。所有设备都监听SCL线，当开始传输时，只有一个设备能在SCL上升沿时发送数据。此外，I2C还包含同步机制，确保数据传输的一致性和准确性。 6. 7位地址模式 I2C支持7位寻址，其中第一字节包含了地址信息。这包括通用呼叫地址、START信号和对兼容性标准（如CBUS）的支持。通过这些位的不同组合，系统可以识别特定的I2C设备。 7. 扩展与增强模式随着版本升级，I2C标准增加了快速模式，显著提升了数据传输速度，使得I2C能够处理更高的数据吞吐量。Hs-Mode进一步增强了性能，尤其适用于需要高速传输的场景。这份I2C使用说明文档提供了全面的指南，涵盖了I2C的基本原理、操作细节、地址管理以及各种模式下的工作方式，对于理解和设计基于I2C的系统具有重要参考价值。无论是硬件工程师还是系统集成者，理解并遵循这些规范都是实现可靠和高效I2C通信的关键。

Philips Semiconductors

The I

C-bus specification

Generation of clock signals on the I

C-bus is always the

responsibility of master devices; each master generates its

own clock signals when transferring data on the bus. Bus

clock signals from a master can only be altered when they

are stretched by a slow-slave device holding-down the

clock line, or by another master when arbitration occurs.

5 GENERAL CHARACTERISTICS

Both SDA and SCL are bi-directional lines, connected to a

positive supply voltage via a current-source or pull-up

resistor (see Fig.3). When the bus is free, both lines are

HIGH. The output stages of devices connected to the bus

must have an open-drain or open-collector to perform the

wired-AND function. Data on the I

C-bus can be

transferred at rates of up to 100 kbit/s in the

Standard-mode, up to 400 kbit/s in the Fast-mode, or up to

3.4 Mbit/s in the High-speed mode. The number of

interfaces connected to the bus is solely dependent on the

bus capacitance limit of 400 pF. For information on

High-speed mode master devices, see Section 13.

6 BIT TRANSFER

Due to the variety of different technology devices (CMOS,

NMOS, bipolar) which can be connected to the I

C-bus,

the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not

fixed and depend on the associated level of V

(see

Section 15 for electrical specifications). One clock pulse is

generated for each data bit transferred.

6.1 Data validity

The data on the SDA line must be stable during the HIGH

period of the clock. The HIGH or LOW state of the data line

can only change when the clock signal on the SCL line is

LOW (see Fig.4).

Fig.3 Connection of Standard- and Fast-mode devices to the I

C-bus.

MBC631

SCLKN1

OUT

SCLK

DATAN1

OUT

DATA

DEVICE 1

SDA (Serial Data Line)

SCL (Serial Clock Line)

SCLKN2

OUT

SCLK

DATAN2

OUT

DATA

DEVICE 2

pull-up

resistors

Philips Semiconductors

The I

C-bus specification

7 TRANSFERRING DATA

7.1 Byte format

Every byte put on the SDA line must be 8-bits long. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an

acknowledge bit. Data is transferred with the most

significant bit (MSB) first (see Fig.6). If a slave can’t

receive or transmit another complete byte of data until it

has performed some other function, for example servicing

an internal interrupt, it can hold the clock line SCL LOW to

force the master into a wait state. Data transfer then

continues when the slave is ready for another byte of data

and releases clock line SCL.

In some cases, it’s permitted to use a different format from

the I

C-bus format (for CBUS compatible devices for

example). A message which starts with such an address

can be terminated by generation of a STOP condition,

even during the transmission of a byte. In this case, no

acknowledge is generated (see Section 10.1.3).

7.2 Acknowledge

Data transfer with acknowledge is obligatory. The

acknowledge-related clock pulse is generated by the

master. The transmitter releases the SDA line (HIGH)

during the acknowledge clock pulse.

The receiver must pull down the SDA line during the

acknowledge clock pulse so that it remains stable LOW

during the HIGH period of this clock pulse (see Fig.7). Of

course, set-up and hold times (specified in Section 15)

must also be taken into account.

Usually, a receiver which has been addressed is obliged to

generate an acknowledge after each byte has been

received, except when the message starts with a CBUS

address (see Section 10.1.3).

When a slave doesn’t acknowledge the slave address (for

example, it’s unable to receive or transmit because it’s

performing some real-time function), the data line must be

left HIGH by the slave. The master can then generate

either a STOP condition to abort the transfer, or a repeated

START condition to start a new transfer.

If a slave-receiver does acknowledge the slave address

but, some time later in the transfer cannot receive any

more data bytes, the master must again abort the transfer.

This is indicated by the slave generating the

not-acknowledge on the first byte to follow. The slave

leaves the data line HIGH and the master generates a

STOP or a repeated START condition.

If a master-receiver is involved in a transfer, it must signal

the end of data to the slave- transmitter by not generating

an acknowledge on the last byte that was clocked out of

the slave. The slave-transmitter must release the data line

to allow the master to generate a STOP or repeated

START condition.

Fig.6 Data transfer on the I

C-bus.

handbook, full pagewidth

MSC608

SDA

SCL

STOP or

repeated START

condition

START or

repeated START

condition

1 2 3 - 8 9

ACK

7812

MSB

acknowledgement

signal from slave

byte complete,

interrupt within slave

clock line held low while

interrupts are serviced

acknowledgement

signal from receiver

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