AVR ATTiny2313v：高性能低功耗微控制器

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"这篇文档详细介绍了 AVR 系列微控制器中的 AVR ATTiny2313v 型号。" AVR ATTiny2313v 是一款基于 AVR RISC（Reduced Instruction Set Computer）架构的微控制器，由Atmel公司（现已被Microchip Technology收购）设计生产。该芯片以其高性能、低功耗的特性而受到广泛应用，特别是在嵌入式系统和小型电子项目中。 1. **AVR RISC 架构** - AVR RISC 架构提供了高效的指令集，大多数指令在单个时钟周期内即可完成执行，这大大提升了处理速度。 - 32个8位通用工作寄存器，使得数据处理更快速，减少了访问内存的次数，提高了性能。 - 完全静态操作，意味着即使在很低的频率下也能保持稳定运行，适应各种应用场景。 2. **内存配置** - **闪存**：包含2KB的在系统自编程闪存（ISP Flash），可承受10,000次写入/擦除循环，用于存储程序代码。 - **EEPROM**：128字节的在系统编程EEPROM，具有100,000次写入/擦除周期，适合存储非易失性数据。 - **SRAM**：128字节的内部静态随机存取内存，用于暂时存储运行时的数据。 3. **外设功能** - **定时器/计数器**：包括一个8位和一个16位定时器/计数器，都带有独立的预分频器和比较模式，可用于脉宽调制（PWM）、定时或事件计数等任务。 - **PWM通道**：四个PWM通道，适用于电机控制和其他功率驱动应用。 - **模拟比较器**：集成的模拟比较器，可用于信号检测和转换。 - **看门狗定时器**：带内部振荡器的可编程看门狗定时器，确保程序稳定运行。 - **USI（通用串行接口）**：提供灵活的通信选项。 - **全双工USART（通用异步收发传输器）**：支持串行通信，如UART协议。 4. **特殊微控制器特性** - **debugWIRE**：内置的在线调试功能，简化了开发过程。 - **在系统编程（ISP）**：可以通过SPI端口进行在系统编程，方便程序更新和调试。 - **外部和内部中断源**：支持多种触发中断的输入，增强了实时响应能力。 - **低功耗模式**：包括低功耗空闲模式、电源下降模式和待机模式，以适应不同场合的节能需求。 - **增强型上电复位电路**：确保系统在启动时处于已知状态。 - **可编程棕色**：可能指的是可编程的布朗中断（Brown-out Detector），当电源电压低于设定阈值时，可以触发复位，防止因电压不稳定导致的问题。 AVR ATTiny2313v 是一个功能强大的微控制器，拥有丰富的外设和内存资源，以及高效能的RISC架构，适用于各种需要低功耗、高性能计算的嵌入式设计。其在系统编程和调试功能使得开发和维护变得更加便捷。

ATtiny2313/V

2543I–AVR–04/06

AVR ATtiny2313

Memories

This section describes the different memories in the ATtiny2313. The AVR architecture

has two main memory spaces, the Data Memory and the Program Memory space. In

addition, the ATtiny2313 features an EEPROM Memory for data storage. All three mem-

ory spaces are linear and regular.

In-System

Reprogrammable Flash

Program Memory

The ATtiny2313 contains 2K bytes On-chip In-System Reprogrammable Flash memory

for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is orga-

nized as 1K x 16.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATtiny2313 Program Counter (PC) is 10 bits wide, thus addressing the 1K program

memory locations. “Memory Programming” on page 162 contains a detailed description

on Flash data serial downloading using the SPI pins.

Constant tables can be allocated within the entire program memory address space (see

the LPM – Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execu-

tion Timing” on page 13.

Figure 8. Program Memory Map

0x0000

0x03F

Program Memory

ATtiny2313/V

2543I–AVR–04/06

• Bits 6..0 – EEAR6..0: EEPROM Address

The EEPROM Address Register – EEAR specify the EEPROM address in the 128 bytes

EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127.

The initial value of EEAR is undefined. A proper value must be written before the

EEPROM may be accessed.

The EEPROM Data Register –

EEDR

• Bits 7..0 – EEDR7..0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to

the EEPROM in the address given by the EEAR Register. For the EEPROM read oper-

ation, the EEDR contains the data read out from the EEPROM at the address given by

EEAR.

The EEPROM Control Register

– EECR

• Bits 7..6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny2313 and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that

will be triggered when writing EEPE. It is possible to program data in one atomic opera-

tion (erase the old value and program the new value) or to split the Erase and Write

operations in two different operations. The Programming times for the different modes

are shown in Table 1. While EEPE is set, any write to EEPMn will be ignored. During

reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set.

Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a

constant interrupt when Non-volatile memory is ready for programming.

Bit 76543210

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 X X 0 0 X 0

Table 1. EEPROM Mode Bits

EEPM1 EEPM0

Programming

Time Operation

0 0 3.4 ms Erase and Write in one operation (Atomic Operation)

0 1 1.8 ms Erase Only

1 0 1.8 ms Write Only

1 1 – Reserved for future use

ATtiny2313/V

2543I–AVR–04/06

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at

the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE

has been written to one by software, hardware clears the bit to zero after four clock

cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the

EEPROM. When EEPE is written, the EEPROM will be programmed according to the

EEPMn bits setting. The EEMPE bit must be written to one before a logical one is writ-

ten to EEPE, otherwise no EEPROM write takes place. When the write access time has

elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is

halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When

the correct address is set up in the EEAR Register, the EERE bit must be written to one

to trigger the EEPROM read. The EEPROM read access takes one instruction, and the

requested data is available immediately. When the EEPROM is read, the CPU is halted

for four cycles before the next instruction is executed. The user should poll the EEPE bit

before starting the read operation. If a write operation is in progress, it is neither possible

to read the EEPROM, nor to change the EEAR Register.

Atomic Byte Programming Using Atomic Byte Programming is the simplest mode. When writing a byte to the

EEPROM, the user must write the address into the EEAR Register and data into EEDR

written) will trigger the erase/write operation. Both the erase and write cycle are done in

one operation and the total programming time is given in Table 1. The EEPE bit remains

set until the erase and write operations are completed. While the device is busy with

programming, it is not possible to do any other EEPROM operations.

Split Byte Programming It is possible to split the erase and write cycle in two different operations. This may be

useful if the system requires short access time for some limited period of time (typically

if the power supply voltage falls). In order to take advantage of this method, it is required

that the locations to be written have been erased before the write operation. But since

the erase and write operations are split, it is possible to do the erase operations when

the system allows doing time-consuming operations (typically after Power-up).

Erase To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writ-

ing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation

only (programming time is given in Table 1). The EEPE bit remains set until the erase

operation completes. While the device is busy programming, it is not possible to do any

other EEPROM operations.

Write To write a location, the user must write the address into EEAR and the data into EEDR.

If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written)

will trigger the write operation only (programming time is given in Table 1). The EEPE bit

remains set until the write operation completes. If the location to be written has not been

erased before write, the data that is stored must be considered as lost. While the device

is busy with programming, it is not possible to do any other EEPROM operations.

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