M25P64 SPI Flash: 64Mbit Development Memory with Low Voltage & High-Speed Interface

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M25P64_SPI_FLASH数据手册介绍了这款即将开发或评估中的64Mbit低电压串行闪存记忆体产品。该存储器具有以下关键特性： 1. 存储容量：64Mbit（8兆位），这意味着它可以存储大量的数据，适用于对存储需求较高的应用。 2. 接口兼容性：支持50MHz SPI（Serial Peripheral Interface）接口，这是一种广泛使用的并行到串行接口标准，便于与其他系统集成。 3. 编程速度：支持快速编程，单个页面最多可写入256字节，典型时间为1.4毫秒，提高了数据写入的效率。 4. 擦除选项：提供多种擦除模式，包括页级擦除（针对512Kbit，即64KB）和块级擦除（覆盖整个64Mbit存储区域），满足不同场景下的数据管理需求。 5. 电源要求：工作电压范围宽广，从2.7V到3.6V，适应于各种低功耗设备。 6. 电子签名：遵循JEDEC标准，提供两字节的标准签名（2017h）以及为了后向兼容性的单字节RES指令签名（16h）。 7. 数据持久性和耐久性：该产品设计用于承受超过100,000次的每区块擦除/编程操作，且能保持至少20年的数据保留时间，保证了长期稳定的数据存储。 8. 封装选项：手册提供了两种封装形式，包括8x6mm的VDFPN8 (ME) 和300mil宽度的SO16 (MF)，这些封装有助于选择最适合项目的尺寸和引脚布局。 9. 图表与连接说明：手册还包括逻辑图、信号名称表、封装连接示意图（如VDFPN和SO连接）等，方便用户理解和使用这款内存芯片。 10. 信号描述：详细解释了SPI接口上的关键信号，如数据输出（Q）、数据输入（D）、时钟（C）、片选（S）和保持信号（HOLD），有助于硬件设计者正确配置接口。 M25P64是一款高效、低功耗且具有长寿命的串行闪存解决方案，适合需要大容量存储和快速数据操作的应用场合。在设计嵌入式系统时，熟悉这些特性和接口规范是至关重要的。

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M25P64

SPI MODES

These devices can be driven by a microcontroller

with its SPI peripheral running in either of the two

following modes:

– CPOL=0, CPHA=0

– CPOL=1, CPHA=1

For these two modes, input data is latched in on

the rising edge of Serial Clock (C), and output data

is available from the falling edge of Serial Clock

(C).

The difference between the two modes, as shown

in Figure 6. , is the clock polarity when the bus

master is in Stand-by mode and not transferring

data:

– C remains at 0 for (CPOL=0, CPHA=0)

– C remains at 1 for (CPOL=1, CPHA=1)

Figure 5. Bus Master and Memory Devices on the SPI Bus

Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

Figure 6. SPI Modes Supported

AI03746D

Bus Master

(ST6, ST7, ST9,

ST10, Others)

SPI Memory

Device

SDO

SDI

SCK

C Q D

SPI Memory

Device

C Q D

SPI Memory

Device

C Q D

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

W HOLD W HOLD W HOLD

AI01438B

MSB

CPHA

CPOL

MSB

M25P64

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OPERATING FEATURES

Page Programming

To program one data byte, two instructions are re-

quired: Write Enable (WREN), which is one byte,

and a Page Program (PP) sequence, which con-

sists of four bytes plus data. This is followed by the

internal Program cycle (of duration t

To spread this overhead, the Page Program (PP)

instruction allows up to 256 bytes to be pro-

grammed at a time (changing bits from 1 to 0), pro-

vided that they lie in consecutive addresses on the

same page of memory.

Sector Erase and Bulk Erase

The Page Program (PP) instruction allows bits to

be reset from 1 to 0. Before this can be applied, the

bytes of memory need to have been erased to all

1s (FFh). This can be achieved either a sector at a

time, using the Sector Erase (SE) instruction, or

throughout the entire memory, using the Bulk

Erase (BE) instruction. This starts an internal

Erase cycle (of duration t

or t

The Erase instruction must be preceded by a Write

Enable (WREN) instruction.

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status

BE) can be achieved by not waiting for the worst

case delay (t

, t

, or t

). The Write In

Progress (WIP) bit is provided in the Status Regis-

ter so that the application program can monitor its

value, polling it to establish when the previous

Write cycle, Program cycle or Erase cycle is com-

plete.

Active Power and Standby Power Modes

When Chip Select (S) is Low, the device is select-

ed, and in the Active Power mode.

When Chip Select (S) is High, the device is dese-

lected, but could remain in the Active Power mode

until all internal cycles have completed (Program,

Erase, Write Status Register). The device then

goes in to the Standby Power mode. The device

consumption drops to I

CC1

Status Register

The Status Register contains a number of status

and control bits that can be read or set (as appro-

priate) by specific instructions.

WIP bit. The Write In Progress (WIP) bit indicates

whether the memory is busy with a Write Status

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the internal Write Enable Latch.

BP2, BP1, BP0 bits. The Block Protect (BP2,

BP1, BP0) bits are non-volatile. They define the

size of the area to be software protected against

Program and Erase instructions.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected mode. In this mode, the non-volatile bits

of the Status Register (SRWD, BP2, BP1, BP0)

become read-only bits.

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