MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
4Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +5V ±5%; V
GND
= 0V; unipolar input mode; 75ksps, f
CLK
= 4.0MHz, external clock (50% duty cycle); MAX187—internal refer-
ence: V
REF
= 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: V
REF
= 4.096V applied to REF pin, 4.7µF capacitor
at REF pin; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
TIMING CHARACTERISTICS
(V
DD
= +5V ±5%, T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
Note 1: Tested at V
DD
= +5V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX187—internal reference, offset nulled; MAX189–external +4.096V reference, offset nulled. Excludes reference errors.
Note 4: Guaranteed by design. Not subject to production testing.
Note 5: External load should not change during conversion for specified ADC accuracy.
Note 6: DC test, measured at 4.75V and 5.25V only.
Note 7: To guarantee acquisition time, t
ACQ
is the maximum time the device takes to acquire the signal, and is also the minimum-
time needed for the signal to be acquired.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL OUTPUT (DOUT)
Output Voltage Low V
OL
I
SINK
= 5mA 0.4
V
I
SINK
= 16mA 0.3
Output Voltage High V
OH
I
SOURCE
= 1mA 4 V
Three-State Leakage Current I
L
V
CS
= 5V
Q10 FA
Three-State Output Capacitance C
OUT
V
CS
= 5V (Note 4)
15 pF
POWER REQUIREMENTS
Supply Voltage V
DD
4.75 5.25 V
Supply Current I
DD
Operating mode
MAX187 1.5 2.5
mA
MAX189 1.0 2.0
Power-down mode 2 10
FA
Power-Supply Rejection
PSR
V
DD
= +5V Q5%; external reference,
4.096V; full-scale input (Note 6)
Q0.06 Q0.5
mV
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Track/Hold Acquisition Time t
ACQ
CS = high (Note7)
1.5 µs
SCLK Fall to Output Data Valid t
DQ
C
LOAD
= 100pF
MAX18_ _C/E 20 150
ns
MAX18_ _M 20 200
CS Fall to Output Enable
t
DV
C
LOAD
= 100pF 100 ns
CS Rise to Output Disable
t
TR
C
LOAD
= 100pF 100 ns
SCLK Clock Frequency t
SCLK
5 MHz
SCLK Pulse Width High t
CH
100 ns
SCLK Pulse Width Low t
CL
100 ns
SCLK Low to CS Fall Setup Time
t
CSO
50 ns
CS Pulse Width
t
CS
500 ns
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