TI PCMD3140-Q1：四通道PDM到TDM/I2S转换器技术规格

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"TI-PCMD3140-Q1.pdf 是一款四通道PDM输入到TDM或I2S输出转换器的详细技术文档。该器件适用于音频处理领域，尤其在麦克风阵列应用中表现出色。" TI的PCMD3140-Q1是一款高性能的四通道PDM（脉冲密度调制）到TDM（时间分复用）或I2S（集成串行音频接口）输出转换器。这款设备的主要特点包括： 1. **四通道PDM麦克风同步转换**：该器件能够同时处理四个PDM信号输入，这意味着它可以连接并处理来自四个不同麦克风的音频数据，这对于构建麦克风阵列和语音识别系统非常有用。 2. **高动态范围转换性能**：PCMD3140-Q1提供高达127-dB动态范围，当输入为5th-order PDM时，而4th-order PDM输入时动态范围也有117 dB。这确保了高质量的声音捕捉和还原能力，减少了噪声和失真。 3. **通道组合模式**：支持两通道组合，组合模式下动态范围仍能达到120 dB，这在需要合并多个麦克风信号的应用中十分关键。 4. **可编程PDM时钟输出**：时钟频率范围从768 kHz到6.144 MHz，可以灵活适应不同的系统需求。 5. **可编程输出采样率**：支持从8 kHz到768 kHz的广泛采样率，适应各种音频应用，如语音通话、音乐播放等。 6. **通道设置灵活性**：包括数字音量控制（范围从-100 dB到+27 dB）、0.1-dB分辨率的增益校准和163-ns分辨率的相位校准，允许精细调整音频信号。 7. **内置功能**：具有麦克风偏置电压或供应电压生成、语音活动检测（VAD）、低延迟信号处理滤波器选择，以及可编程高通滤波器和二阶数字滤波器。 8. **I2C控制**：通过I2C接口进行设备配置和控制，简化了系统集成。 9. **高性能音频PLL**：集成的PLL（锁相环）提高了时钟精度，确保音频信号的稳定传输。 10. **自动时钟分频器设置**：自动配置时钟分频器，以优化性能并降低设计复杂性。 11. **音频串行数据接口**：支持TDM、I2S和左对齐（LJ）格式，数据宽度可选16位、20位、24位或32位，提供高度的灵活性以适应不同的系统架构。 TI-PCMD3140-Q1是一款针对高精度音频处理设计的专业转换器，适用于需要多通道麦克风输入和灵活数字音频输出的多种应用场景，如智能家居、语音助手、智能汽车和专业音频设备等。其丰富的特性集和可编程性使其成为开发高效、高质量音频解决方案的理想选择。

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Serial Interfaces

This device has two serial interfaces: control and audio data. The control serial interface is used for device

configuration. The audio data serial interface is used for transmitting audio data to the host device.

7.3.1.1 Control Serial Interfaces

The device control registers can be accessed using I

C communication to the device. The device operates with

a fixed I

C address and can be configured using this address.

7.3.1.2 Audio Serial Interfaces

Digital audio data flows between the host processor and the PCMD3140-Q1 on the digital audio serial interface

(ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I

or left-justified protocols format, programmable data length options, very flexible master-slave configurability for

bus clock lines, and the ability to communicate with multiple devices within a system directly.

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The bus protocol TDM, I

S, or left-justified (LJ) format can be selected by using the ASI_FORMAT[1:0]

(P0_R7_D[7:6]) register bits. As shown in Table 7-2 and Table 7-3, these modes are all most significant byte

(MSB)-first, pulse code modulation (PCM) data format, with the output channel data word-length programmable

as 16, 20, 24, or 32 bits by configuring the ASI_WLEN[1:0] (P0_R7_D[5:4]) register bits.

Table 7-2. Audio Serial Interface Format

P0_R7_D[7:6] : ASI_FORMAT[1:0] AUDIO SERIAL INTERFACE FORMAT

00 (default) Time division multiplexing (TDM) mode

01 Inter IC sound (I

S) mode

10 Left-justified (LJ) mode

11 Reserved (do not use this setting)

Table 7-3. Audio Output Channel Data Word-Length

P0_R7_D[5:4] : ASI_WLEN[1:0] AUDIO OUTPUT CHANNEL DATA WORD-LENGTH

00 Output channel data word-length set to 16 bits

01 Output channel data word-length set to 20 bits

10 Output channel data word-length set to 24 bits

11 (default) Output channel data word-length set to 32 bits

The frame sync pin, FSYNC, is used in this audio bus protocol to define the beginning of a frame and has the

same frequency as the output data sample rates. The bit clock pin, BCLK, is used to clock out the digital audio

data across the serial bus. The number of bit-clock cycles in a frame must accommodate multiple device active

output channels with the programmed data word length.

A frame consists of multiple time-division channel slots (up to 64) to allow all output channel audio data

transmissions to complete on the audio bus by a device or PCMD3140-Q1 and other Audio devices sharing the

same bus. The device supports up to four output channels that can be configured to place their audio data on

bus slot 0 to slot 63. Table 7-4 lists the output channel slot configuration settings. In I

S and LJ mode, the slots

are divided into two sets, left-channel slots and right-channel slots, as described in the Section 7.3.1.2.2 and

Section 7.3.1.2.3 sections.

Table 7-4. Output Channel Slot Assignment Settings

P0_R11_D[5:0] : CH1_SLOT[5:0] OUTPUT CHANNEL 1 SLOT ASSIGNMENT

00 0000 = 0d (default) Slot 0 for TDM or left slot 0 for I

S, LJ.

00 0001 = 1d Slot 1 for TDM or left slot 1 for I

S, LJ.

… …

01 1111 = 31d Slot 31 for TDM or left slot 31 for I

S, LJ.

10 0000 = 32d Slot 32 for TDM or right slot 0 for I

S, LJ.

… …

11 1110 = 62d Slot 62 for TDM or right slot 30 for I

S, LJ.

11 1111 = 63d Slot 63 for TDM or right slot 31 for I

S, LJ.

Similarly, the slot assignment setting for output channel 2 to channel 4 can be done using the CH2_SLOT

(P0_R12) to CH8_SLOT (P0_R18) registers, respectively.

The slot word length is the same as the output channel data word length set for the device. The output channel

data word length must be set to the same value for all PCMD3140-Q1 devices if all devices share the same ASI

bus in a system. The maximum number of slots possible for the ASI bus in a system is limited by the available

bus bandwidth, which depends upon the BCLK frequency, output data sample rate used, and the channel data

word length configured.

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The device also includes a feature that offsets the start of the slot data transfer with respect to the frame sync by

up to 31 cycles of the bit clock. Table 7-5 lists the programmable offset configuration settings.

Table 7-5. Programmable Offset Settings for the ASI Slot Start

P0_R8_D[4:0] : TX_OFFSET[4:0] PROGRAMMABLE OFFSET SETTING FOR SLOT DATA TRANSMISSION START

0 0000 = 0d (default) The device follows the standard protocol timing without any offset.

0 0001 = 1d

Slot start is offset by one BCLK cycle, as compared to standard protocol timing.

For I

S or LJ, the left and right slot start is offset by one BCLK cycle, as compared to

standard protocol timing.

...... ......

1 1110 = 30d

Slot start is offset by 30 BCLK cycles, as compared to standard protocol timing.

For I

S or LJ, the left and right slot start is offset by 30 BCLK cycles, as compared to

standard protocol timing.

1 1111 = 31d

Slot start is offset by 31 BCLK cycles, as compared to standard protocol timing.

For I

S or LJ, the left and right slot start is offset by 31 BCLK cycles, as compared to

standard protocol timing.

The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio

data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using

the FSYNC_POL (P0_R7_D3) register bit. Similarly, the device can invert the polarity of the bit clock pin, BCLK,

which can be set using the BCLK_POL (P0_R7_D2) register bit.

7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface

In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data

first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and

each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK.

Figure 7-1 to Figure 7-4 illustrate the protocol timing for TDM operation with various configurations.

N-1

2 1 0

N-2 N-3 N-1 N-2 N-3

2 1 0 N-1

N-2 N-3

2 1 0

Slot-0

(Word Length : N)

Slot-1

(Word Length : N)

Slot-2 to Slot-7

(Word Length : N)

N-1

2 1 0

N-2 N-3

Slot-0

(Word Length : N)

FSYNC

BCLK

SDOUT

Sample

(n+1)

Sample

Figure 7-1. TDM Mode Standard Protocol Timing (TX_OFFSET = 0)

2 1 0

N-1 N-1 N-2 N-3

2 1 0 N-1

N-2 N-3

2 1 0

Slot-0

(Word Length : N)

Slot-1

(Word Length : N)

Slot-2 to Slot-7

(Word Length : N)

2 1 0

N-1

Slot-0

(Word Length : N)

Sample

(n+1)

Sample

TX_OFFSET = 2

FSYNC

BCLK

SDOUT

Figure 7-2. TDM Mode Protocol Timing (TX_OFFSET = 2)

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Sample

(n+1)

Sample

FSYNC

BCLK

SDOUT

2 1 0

N-1 N-1 N-2 N-3

2 1 0 N-1

N-2 N-3

0 N-1 N-2

Slot-0

(Word Length : N)

Slot-1

(Word Length : N)

Slot-2 to Slot-7

(Word Length : N)

2 1 0

N-1

Slot-0

(Word Length : N)

TX_OFFSET = 2

2 1 0

Figure 7-3. TDM Mode Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 2)

N-1

2 1 0

N-2 N-3 N-1 N-2 N-3

2 1 0 N-1

N-2 N-3

2 1 0

Slot-0

(Word Length : N)

Slot-1

(Word Length : N)

Slot-2 to Slot-7

(Word Length : N)

N-1

2 1 0

N-2 N-3

Slot-0

(Word Length : N)

FSYNC

BCLK

SDOUT

Sample

(n+1)

Sample

Figure 7-4. TDM Mode Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)

For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than

or equal to the number of active output channels times the programmed word length of the output channel data.

The device supports FSYNC as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well. For a

higher BCLK frequency operation, using TDM mode with a TX_OFFSET value higher than 0 is recommended.

7.3.1.2.2 Inter IC Sound (I

S) Interface

The standard I

S protocol is defined for only two channels: left and right. The device extends the same protocol

timing for multichannel operation. In I

S mode, the MSB of the left slot 0 is transmitted on the falling edge of

BCLK in the second cycle after the falling edge of FSYNC. Immediately after the left slot 0 data transmission, the

remaining left slot data are transmitted in order. The MSB of the right slot 0 is transmitted on the falling edge of

BCLK in the second cycle after the rising edge of FSYNC. Immediately after the right slot 0 data transmission,

the remaining right slot data are transmitted in order. FSYNC and each data bit is transmitted on the falling edge

of BCLK. Figure 7-5 to Figure 7-8 illustrate the protocol timing for I

S operation with various configurations.

1 0

N-1 N-2 N-1 N-2

1 0

Left

Slot-0

(Word Length : N)

Left

Slot-2 to Slot-3

(Word Length : N)

1 0

N-1 N-2

FSYNC

BCLK

SDOUT

Sample

(n+1)

Sample

1 0

N-1 N-1 N-2

1 0

Right

Slot-0

(Word Length : N)

Right

Slot-2 to Slot-3

(Word Length : N)

Left

Slot-0

(Word Length : N)

Figure 7-5. I

S Mode Standard Protocol Timing (TX_OFFSET = 0)

1 0

N-1 N-1 N-2

1 0

Left

Slot-0

(Word Length : N)

Left

Slot-2 to Slot-3

(Word Length : N)

1 0

N-1

FSYNC

BCLK

SDOUT

Sample

(n+1)

Sample

1 0

N-1 N-1

1 0

Right

Slot-0

(Word Length : N)

Right

Slot-2 to Slot-3

(Word Length : N)

Left

Slot-0

(Word Length : N)

TX_OFFSET = 1

Figure 7-6. I

S Protocol Timing (TX_OFFSET = 1)

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1 0

N-1 N-2 N-1 N-2

0 N-1

Left

Slot-1 to Slot-3

(Word Length : N)

1 0

N-1 N-2

FSYNC

BCLK

SDOUT

Sample

(n+1)

Sample

1 0

N-1 0 N-1

1 0

Right

Slot-1 to Slot-3

(Word Length : N)

Left

Slot-0

(Word Length : N)

1 0

N-1 N-2

Figure 7-7. I

S Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)

1 0

N-1 N-2 N-1 N-2

1 0

Left

Slot-0

(Word Length : N)

Left

Slot-2 to Slot-3

(Word Length : N)

1 0

N-1 N-2

FSYNC

BCLK

SDOUT

Sample

(n+1)

Sample

1 0

N-1 N-1 N-2

1 0

Right

Slot-0

(Word Length : N)

Right

Slot-2 to Slot-3

(Word Length : N)

Left

Slot-0

(Word Length : N)

Figure 7-8. I

S Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)

For proper operation of the audio bus in I

S mode, the number of bit clocks per frame must be greater than or

equal to the number of active output channels (including left and right slots) times the programmed word length

of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater

than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC high

pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots

times the data word length configured.

7.3.1.2.3 Left-Justified (LJ) Interface

The standard LJ protocol is defined for only two channels: left and right. The device extends the same protocol

timing for multichannel operation. In LJ mode, the MSB of the left slot 0 is transmitted in the same BCLK

cycle after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK.

Immediately after the left slot 0 data transmission, the remaining left slot data are transmitted in order. The MSB

of the right slot 0 is transmitted in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data

bit is transmitted on the falling edge of BCLK. Immediately after the right slot 0 data transmission, the remaining

right slot data are transmitted in order. FSYNC is transmitted on the falling edge of BCLK. Figure 7-9 to Figure

7-12 illustrate the protocol timing for LJ operation with various configurations.

1 0

N-1 N-2 N-1 N-2

1 0

Left

Slot-0

(Word Length : N)

Left

Slot-2 to Slot-3

(Word Length : N)

1 0

N-1 N-2

BCLK

SDOUT

Sample

(n+1)

Sample

1 0

N-1 N-1 N-2

1 0

Right

Slot-0

(Word Length : N)

Right

Slot-2 to Slot-3

(Word Length : N)

Left

Slot-0

(Word Length : N)

FSYNC

Figure 7-9. LJ Mode Standard Protocol Timing (TX_OFFSET = 0)

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