TMS320C66x SoC上的多核DSP算法实时实现

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"《Multicore DSP From Algorithms to Real-time Implementation》是Naim Dahnoun在2018年出版的一本关于多核DSP技术的书籍，主要关注如何在TMS320C66x SoC（系统级芯片）上实现从算法到实时应用的转换。这本书由John Wiley & Sons Ltd发行，强调了多核数字信号处理器在实时系统中的应用和实现细节。" 正文：多核数字信号处理器(DSP)已经成为现代高性能计算和实时处理的关键技术。本书《Multicore DSP From Algorithms to Real-time Implementation》深入探讨了这一领域，特别关注了如何在德州仪器(TI)的TMS320C66x SoC平台上将算法高效地转化为实时运行的系统。Naim Dahnoun，来自英国布里斯托大学的作者，以其专业知识为读者提供了一条从理论到实践的清晰路径。多核架构的优势在于它能够并行处理多个任务，提高系统的吞吐量和效率。在TMS320C66x SoC中，这种架构被设计用来满足高带宽、低延迟的实时应用需求，如通信、图像处理和音频应用。书中详细介绍了如何利用这些硬件特性来优化算法性能，包括任务分配、负载平衡和通信管理。本书涵盖了以下关键知识点： 1. **多核处理器基础**：解释多核架构的基本概念，包括并行处理、并发执行以及它们如何提升性能。 2. ** DSP算法设计**：讨论适用于多核环境的算法设计原则，如数据流图分析、并行化策略和算法分解。 3. **实时系统**：阐述实时系统的需求和挑战，包括确定性和响应时间的重要性。 4. **TMS320C66x SoC架构**：详细介绍该芯片的硬件结构，如处理单元、内存配置和片上通信网络。 5. **编程与调试**：介绍如何编写高效的多核代码，以及使用调试工具进行性能分析和优化。 6. **案例研究**：通过实际示例展示多核DSP的实现过程，帮助读者理解并掌握多核系统设计技巧。 7. **性能评估**：讲解性能度量标准和评估方法，以确保系统满足实时性和效率要求。 8. **最佳实践**：提供设计和实现多核DSP系统的实用建议，帮助工程师避免常见的陷阱和错误。 9. **知识产权(IoP)和软件复用**：探讨如何利用已有的IP模块和软件组件来加速开发过程。通过这本书，读者不仅可以学习到多核DSP的基础知识，还能获得在实际项目中应用这些知识的实践经验。无论是研究人员、工程师还是学生，都能从中受益，提升他们在多核实时系统设计上的技能。同时，书中提供的链接（http://www.wiley.com/go/permissions）可以帮助获取重用书中材料的许可信息，尊重和遵守版权法。

19 Hough transform 591

19.1 Introduction 591

19.2 Theory 591

19.3 Limits of r and θ 593

19.4 Hough transform implementation 595

19.5 Laboratory experiment 596

19.6 Conclusion 603

References 603

20 Stereo vision implementation 604

20.1 Introduction 604

20.2 Algorithm for performing depth calculation 605

20.3 Cost functions 606

20.4 Implementation 607

20.4.1 Laboratory experiment 610

20.4.1.1 SAD implementation 610

20.4.1.2 NCC implementation 611

20.4.1.3 ZNCC implementation 611

20.5 Conclusion 613

References 616

Index 617

Contents xvii

Preface

Today’s many applications, such as medical, high-end imaging, high-performance computing

and core networking, are facing increasing challenges in terms of data traffic, processing power

and device- to-device communication . These put a high demand on the processor(s) and asso-

ciated software and lead to processor manufacturers sustaining Moore’s law by introducing

multicore processors. Texas Instruments, with its leading-edge technology, introduced the mul-

ticore System-on-Chip (SoC) architecture family of processors to address these issues. As will be

shown in this book, Texas Instruments introduced innovations at many levels, such as: powerful

CPUs that support both fixed- and floating-point arithmetic (instruction by instruction) that can

achieve more than 40G multiplications/core, a Navigator that enables direct communication

between cores and memory access that removes data movement bottlenecks, a Hyperlink inter-

face and advanced development tools.

The challenge is not only how many cores you can put on a piece of silicon, the processing

power of each core and how fast they can communicate, but also in the programming model

and ease of use. Unfortunately, programming models are not developed sufficiently to handle

several cores. The improvement in performance gained by the use of a multicore processor

depends very much on the application and software used. C and C++, which are commonly used

in embedded systems, do not support partitioning and, therefore, porting sequential code to

multicore is not trivial. In this book, it will be shown this complexity is alleviated by using:

OpenMP, which is an Application Programming Interface (API) that supports multiplatform

shared multiprocessing programming in C, C++ and Fortran; Open Computing Language

(OpenCL); or the Inter-Processor Communication (IPC).

This book will help to innovate by making the reader understand the KeyStone SoC architec-

tures, the development tools including debugging and various programming models with tested

examples, and also help to broaden the knowledge by critically analysing each element (see

Table of Contents) and understanding how these elements are working together. With the sheer

number of practical examples and references provided, the reader will be able to quickly develop

applications, take advantage of maximum performance and functionality of the processors, be

able to easily use the tools to develop and debug applications and find the relevant references to

pertinent material. Real-time multicore audio and video applications are provided. Applications

will be based on TI’s Multicor e Software Development Kit (MCSDK), hand-optimised code,

OpenMP, OpenCL and IPC.

Due to the sheer amount of documentation available, some information is either referred to or

reproduced to avoid discontinuity and misinterpretation.

This book is divided into 20 chapters. Chapters 1 to 15 deal with the hardware and software

issues, and Chapters 16 to 20 deal with applications. Most of the concepts are backed up with

laboratory experiments and demos that have been thoroughly tested.

xviii

Chapter 1 Introduction: This introductory chapter provides the reader with general knowledge

on multicore processors and their applications; gives a brief comparison between digital signal

processor (DSP) SoCs, field-programmable gate arrays (FPGAs), graphic processors and CPUs;

illustrates the challenges associated with multicore; and provides an up-to-date TMS320 road-

map showing the evolution of TI’s DSP chips in terms of processing power.

Chapter 2 The TMS320C66x architecture overview: This chapter comprehensively describes

the TMS320C66x architecture. This includes a detailed description of the DSP CorePacs and an

overview of the peripherals, and it introduces some useful instructions and an overview of the

memory organisation.

Chapter 3 Software development tools and the TMS320C6678 EVM: This chapter describes

the software development tools that are required for testing the applications used in this book.

It provides a step-by-step guide to the installation and use of the Code Composer Studio (CCS).

Chapter 4 Numerical issues: This chapter explains how fixed and floating points are repre-

sented and how to handle binary arithmetic. It provides examples showing how to display var-

ious data formats using the CCS.

Chapter 5 Software optimisation: This chapter discusses the different levels of optimisation

for multicore and shows how code can be optimised for a DSP core. This chapter also shows

how to use intrinsics and interface C language with intrinsics and assembly code. Multiple exam-

ples showing how to optimise code by hand and using the tools are provided.

Chapter 6 The TMS320C66x interrupts: This chapter shows how the interrupt controller

events and the Chip-level Interrupt Controller work and how to program them to respond

to events. The examples given use the general-purpose input–output (GPIO) pins to provide

the interrupts.

Chapter 7 Real-time operating system: TI-RTOS: This chapter is divided into three main sec-

tions: (1) a real-time scheduler that is composed of the hardware and software interrupts, the

task, the idle, clock and timer functions, synchronisation and events; (2) dynamic memory man-

agement; and (3) laboratory experiments.

Chapter 8 Enhanced Direct Memory Access (EDMA3) Controller: This chapter describes in

detail the operation of the EDMA and provides examples with simple transfer, chaining transfer

and linked transfer.

Chapter 9 Inter-Processor Communication (IPC): This chapter explains the need for IPC and

describes the notify module, the messageQ, the ListMP module, the Multi-processor Memory

Allocation, the transport mechanism and laboratory examples.

Chapter 10 Single and multicore debugging: This chapter introduces the need for debugging

and describes the debug architecture that includes trace, Advanced Event Triggering and the

Unified Breakpoint Manager. This chapter also describes the Unified Instrumentation Architec-

ture, debugging with the System Analyzer tools, instrumentation with TI-RTOS and CCS and

laboratory experiments.

Chapter 11 Bootloader for Keystone I and Keystone II: This chapter introduces the boot

process for both the KeyStone I and KeyStone II, and provides laboratory experiments for both

devices.

Chapter 12 Introduction to OpenMP : This chapter introduces the concept behind OpenMP

and divides the content into three main sections: (1) work sharing, (2) data sharing and (3)

Preface xix

synchronisation. Various examples with both KeyStone I and II are provided. For the KeyStone

II, an example is implemented with OpenMP with the accelerator model.

Chapter 13 Introduction to OpenCL for the KeyStone II: In this chapter, another program-

ming model called Open Computing Language (OpenCL) is introduced. This chapter will

emphasise the OpenCL for the KeyStone rather than other devices. This chapter will show that

OpenCL is easy to use since the programmer does not need to deal with details of communi-

cation between DSP cores or between the ARM and the DSP, which may be a daunting task.

Chapter 14 Multicore Navigator: This chapter shows how the Multicore Navigator can pro-

vide a high-speed packed data transfer to enhance CorePac to accelerator/peripheral data move-

ments, core-to-core data movements, inter-core communication and synchronisation without

loading the CorePacs. Examples are also provided.

Chapter 15 FIR filter implementation: The purpose of this chapter is twofold. Primarily, it

shows how to design an FIR filter and implement it on the TMS320C66x processor; and, sec-

ondly, it shows how to optimise the code as discussed in Chapter 3. This chapter discusses the

interface between C and assembly, how to use intrinsics, and how to put into practice material

that has been covered in the previous chapters.

Chapter 16 IIR filter implementation: This chapter introduces the IIR filters and describes

two popu lar design methods: the bilinear and the impulse invariant methods. Step by step, this

chapter shows the procedures necessary to implement typical IIR filters specified by their trans-

fer functions. Finally, this chapter provides complete implementation of an IIR filter in

C language, assembly and linear assembly, and shows how to interface C with linear assembly.

Chapter 17 Adaptive filter implementation: This chapter starts by introducing the need for an

adaptive filter in communications. It then shows how to calculate the filter coefficients using the

mean squared error (MSE) criterion, exposes the least mean squares (LMS) algorithm and,

finally, shows how the LMS algorithm is implemented in both C and assembly.

Chapter 18 FFT implementation: This chapter shows a derivation of an FFT algorithm and

shows its implementation in C language. To improve the performance, the ping-pong EDMA

has been used.

Chapter 19 Hough transform: This chapter shows the basic mathematics behind the Hough

transform for detecting straight lines and how to implement it. This chapter also shows how to

increase the performance by looking at the algorithm and minimising the number of operation s

required, and how to use the graphical display using the Code Composer Studio.

Chapter 20 Stereo vision implementation: This chapter shows the principle behind the stereo

vision system and hig hlights different levels of optimisations for achieving real-time perfor-

mance. Some techniques for reducing the processing time for calculating the disparity values

for automotive applications are also introduced.

Prefacexx

Acknowledgements

I didn’t expect that writing another book would be challenging, considering that I have written

previous material. This was mainly due to the fast-moving technology and because systems are

getting more complex, but I had to keep up with it. Putting all knowledge gained in a simple form

and sharing it give me great satisfaction.

My first thanks go to the Engineer to Engineer (e2e.ti.com) community that I found extremely

generous and very helpful.

I am indebted to Cathy Wicks, Jocken Schyma, Jason Brand, Garry Clarkson and Rogerio

Almeida, the key motivators and initiators for writing this book.

I would like to express my gratitude to the following reviewers for their insightful suggestions

and comments: Pekka Varis, Dave Bell, Eric Stotzer, John Smrstik, Jennifer Stadelmann, Ran

Katzur, Steve Preissig, Naga Chandrashekar, Greg Peake and Filip Moerman.

I ow e my thanks to Professor John Rarity, Professor Andy Nix, Professor Dave Cliff, Professor

David May, Dr Richard Nock, Dr Ross Xi, Dr Sergey Vityazev, Mr James Webley and all my col-

leagues at the Faculty of Engineering, University of Bristol, for their encouragement and support.

I also thank all my students, and in particular Scott Tancock, Han Cui, Aleksandar Stanoev,

Victor Prokhorov, Aliaksei Mikhailiuk, Akmal Ahmed, Ranger Fan, Elliott Worsey and Charles

Khoury who were always eager to explore challenging issues, verify and test applications.

My thanks to my friends Professor Hamdani Abdelsalam, Judge Shamin and his wife Shabina,

Hernandez Paul and his wife Khansa, Mr Baris Tan yeri, Mr Karaborek Yunus, Dr Tila Fai,

Mr Ghoul Amar and Dr Seti Chenafa for their continuous support and friendship.

To my friend Gene Frantz, ‘the father of DSP’, who wrote the Foreword to my book and who

has been a great inspiration to me.

Finally, many thanks to Ruth Thomas for her kindness in reading the whole manuscript and

providing feedback, and Alex King and Preethi Belkese from Wiley who were very easy to deal

with, encouraging and supportive.

Naim Dahnoun

Naim.Dahnoun@Bristol.ac.uk

xxi

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