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首页"瑞萨RH850 U2A用户手册:硬件指南(2021年10月更新)"
"瑞萨RH850 U2A用户手册:硬件指南(2021年10月更新)"
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瑞萨RH850 U2A用户手册是一份详细介绍瑞萨微控制器RH850 U2A系列的硬件信息的手册。该手册的目标用户是Robert Bosch GmbH RH850/U2A-EVA Group,旨在帮助他们了解并操作该款微控制器。
该用户手册的版本为Rev.1.20,于2021年10月发布。手册包含了关于RH850 U2A系列产品及其规格的详细信息。手册中的所有材料,包括产品和产品规格,均代表了产品发布时的信息,并且可能会在未经瑞萨电子公司通知的情况下发生变化。因此,用户需要及时查阅瑞萨电子公司以各种方式发布的最新信息,以获取准确的产品信息。
瑞萨RH850 U2A用户手册主要分为硬件部分。在硬件部分中,手册详细介绍了RH850 U2A微控制器的硬件架构、功能模块和各种接口。它还提供了关于如何设计和连接外部硬件设备的指导,以及如何利用RH850 U2A的各种功能和特性来实现特定的应用需求。
手册还包含了关于RH850 U2A微控制器开发环境的介绍和配置指南。它提供了使用RH850 U2A的软件工具和开发套件的详细说明,以及如何进行软件开发和调试的指导。此外,手册还提供了一些示例代码和开发案例,以帮助用户更好地理解和应用RH850 U2A微控制器。
瑞萨RH850 U2A用户手册的编写结构清晰、语言简洁明了。手册的内容既包含了基础知识,也涵盖了高级应用方面的内容,适合各种技术水平的用户使用。手册还提供了详尽的索引和目录,以方便用户快速查找和定位所需信息。
总的来说,瑞萨RH850 U2A用户手册是一份全面、详细的指南,全面介绍了RH850 U2A微控制器的硬件信息和开发环境。它为用户提供了必要的技术支持和指导,帮助他们更好地了解和应用RH850 U2A微控制器,实现各种应用需求。用户可以通过查阅手册中的信息,快速上手并掌握RH850 U2A微控制器的使用技巧,提高开发效率。
Attn. Robert Bosch GmbH
Section 4 Address Space............................................................................................. 545
4.1 Overview..................................................................................................................................... 545
4.2 Address Space Viewed from Each Bus Master .......................................................................... 549
4.2.1 Space in which instructions can be fetched...................................................................... 549
4.2.2 Data Space Accessible by CPUs ..................................................................................... 549
4.2.3 Data Space Accessible by DMA modules ........................................................................ 550
4.2.4 Data Space Accessible by H-Bus modules ...................................................................... 550
4.3 Error notification for an access to unmapped area ..................................................................... 551
4.3.1 Unmapped Code Flash area access error........................................................................ 551
4.3.2 Unmapped Cluster RAM area access error...................................................................... 554
4.3.3 Unmapped Local RAM area access error ........................................................................ 554
4.3.4 Unmapped CPU peripheral area access error ................................................................. 554
4.3.5 Details of P-Bus area........................................................................................................ 555
4.3.6 Details of H-Bus area ....................................................................................................... 582
4.3.7 Details of I-Bus area......................................................................................................... 583
4.3.8 Debug area....................................................................................................................... 584
4.3.9 Other area ........................................................................................................................ 586
4.4 Related Requirements ............................................................................................................... 587
Section 5 Operating Modes ......................................................................................... 588
5.1 Features...................................................................................................................................... 588
5.1.1 Normal Operation Mode ................................................................................................... 589
5.1.2 User Boot Mode 0/1.......................................................................................................... 589
5.1.3 Serial Programming Mode 0/1.......................................................................................... 589
5.1.4 Boundary Scan Mode....................................................................................................... 589
5.2 Input Pins.................................................................................................................................... 589
5.3 Interrupt Requests and Error Notifications.................................................................................. 590
5.4 Register Description ................................................................................................................... 591
5.4.1 List of Registers................................................................................................................ 591
5.4.2 Reset of Registers............................................................................................................ 591
5.4.3 MODE — Mode Register.................................................................................................. 592
5.5 Mode Error.................................................................................................................................. 593
5.6 Related Requirements ............................................................................................................... 594
Section 6 Interrupts...................................................................................................... 595
6.1 Features of Interrupt Units.......................................................................................................... 595
6.1.1 Units and Channels .......................................................................................................... 595
6.1.2 Register Base Address..................................................................................................... 597
6.1.3 Clock Supply..................................................................................................................... 597
6.1.4 Reset Sources.................................................................................................................. 598
6.1.5 External Input/Output Signals........................................................................................... 598
6.1.6 Edge Detection Configuration........................................................................................... 599
6.2 Overview..................................................................................................................................... 600
6.2.1 Outline .............................................................................................................................. 600
Attn. Robert Bosch GmbH
6.2.2 Functional Overview......................................................................................................... 601
6.2.3 Interrupt Sources.............................................................................................................. 602
6.2.4 Block Diagram .................................................................................................................. 604
6.3 Registers..................................................................................................................................... 605
6.3.1 List of Registers................................................................................................................ 605
6.3.2 EIC0 to EIC767 — EI Level Interrupt Control Register 0 to 767....................................... 607
6.3.3 IMR0 to IMR23 — EI Level Interrupt Mask Register 0 to 23 ............................................ 609
6.3.4 EIBD0 to EIBD31 — EI Level Interrupt Bind Register 0 to 31 .......................................... 610
6.3.5 EIBD32 to EIBD767 — EI Level Interrupt Bind Register 32 to 767 .................................. 611
6.3.6 FIBD — FE Level Interrupt Bind Register......................................................................... 613
6.3.7 EEIC0 to EEIC767 — Extended EI Level Interrupt Control Register 0 to 767.................. 614
6.3.8 IHVCFG — INTC1 Virtualization Configuration Register.................................................. 616
6.3.9 EIBG — BGEIINT Priority Level Setting Register............................................................. 617
6.3.10 I2EIBG0 to I2EIBG3 — INTC2 BGEIINT Priority Level Setting Register.......................... 618
6.3.11 FIBG — BGFEINT Channel Mask Setting Register ......................................................... 619
6.3.12 SINTR0 to SINTR3 — Software Interrupt Register .......................................................... 620
6.3.13 PINTn + x — Peripheral Interrupt Status Register ........................................................... 621
6.3.14 PINTCLRn + x — Peripheral Interrupt Status Clear Register........................................... 622
6.3.15 FENMIF — FENMI Status Register.................................................................................. 623
6.3.16 FENMIC — FENMIC Status Clear Register ..................................................................... 624
6.3.17 FEINTF — FEINT Status Register ................................................................................... 625
6.3.18 FEINTMSK — FEINT Event Mask Register ..................................................................... 626
6.3.19 FEINTC — FEINT Status Clear Register ......................................................................... 627
6.4 Interrupt Operation...................................................................................................................... 628
6.4.1 Level Interrupts................................................................................................................. 628
6.4.2 Inter-Processor Interrupts................................................................................................. 628
6.4.3 Broadcast Interrupts ......................................................................................................... 628
6.4.4 Software Interrupts ........................................................................................................... 628
6.4.5 DTS Interrupt Merge Function.......................................................................................... 628
6.4.6 Priority Level Handling...................................................................................................... 629
6.5 Interrupt Processing Flow........................................................................................................... 630
6.5.1 Level Interrupt Processing Flow ....................................................................................... 630
6.5.2 FENMI Processing Flow ................................................................................................... 631
6.5.3 External Interrupt Processing Flow................................................................................... 632
6.5.4 Broadcast Interrupt Processing Flow................................................................................ 634
6.5.5 Software Interrupt Processing Flow.................................................................................. 635
6.5.6 DTS Interrupt Processing Flow......................................................................................... 636
6.5.7 MSPI Interrupt Processing Flow ....................................................................................... 638
6.6 Interrupt Response Times .......................................................................................................... 640
6.7 Related Requirements ............................................................................................................... 642
Section 7 sDMA Controller (sDMAC)........................................................................... 643
7.1 Features sDMAC for RH850/U2A-EVA ...................................................................................... 643
7.1.1 Number of Units................................................................................................................ 643
7.1.2 Register Base Addresses................................................................................................. 643
Attn. Robert Bosch GmbH
7.1.3 Clock Supply..................................................................................................................... 643
7.1.4 Interrupts Requests and Error Notifications...................................................................... 644
7.1.5 sDMAC Transfer Requests............................................................................................... 647
7.1.6 Reset Sources.................................................................................................................. 647
7.2 Overview..................................................................................................................................... 648
7.2.1 Functional Overview......................................................................................................... 648
7.2.2 Block Diagram .................................................................................................................. 649
7.3 Registers of sDMAC ................................................................................................................... 651
7.3.1 List of Registers................................................................................................................ 651
7.3.2 DMAjESTA — DMA Address Error Interrupt Status Register........................................... 653
7.3.3 DMAjISTA — DMA Channel Interrupt Status Register..................................................... 654
7.3.4 DMAjCHPRI — DMA Channel Request Priority Register................................................. 655
7.3.5 DMAjOR — DMA Operation Register............................................................................... 656
7.3.6 DMAjCHRST — DMA Channel Reset Register................................................................ 657
7.3.7 DMAjCM_n — DMA Channel Master Setting Register n.................................................. 658
7.3.8 DMAjSAR_n — DMA Source Address Register n............................................................ 659
7.3.9 DMAjDAR_n — DMA Destination Address Register n..................................................... 660
7.3.10 DMAjTSR_n — DMA Transfer Size Register n ................................................................ 661
7.3.11 DMAjTSRB_n — DMA Transfer Size Register B n .......................................................... 662
7.3.12 DMAjTMR_n — DMA Transfer Mode Register n.............................................................. 663
7.3.13 DMAjCHCR_n — DMA Channel Control Register n ........................................................ 665
7.3.14 DMAjCHSTP_n — DMA Channel Suspend Register ....................................................... 667
7.3.15 DMAjCHSTA_n — DMA Channel Status Register n........................................................ 668
7.3.16 DMAjCHFCR_n — DMA Channel Flag Clear Register n ................................................. 670
7.3.17 DMAjGIAI_n — DMA Gather Inner Address Increment Register n .................................. 672
7.3.18 DMAjGOAI_n — DMA Gather Outer Address Increment Register n................................ 672
7.3.19 DMAjSIAI_n — DMA Scatter Inner Address Increment Register n .................................. 673
7.3.20 DMAjSOAI_n — DMA Scatter Outer Address Increment Register n................................ 673
7.3.21 DMAjSGST_n — DMA Scatter Gather Status Register n ................................................ 674
7.3.22 DMAjSGCR_n — DMA Scatter Gather Control Register n .............................................. 675
7.3.23 DMAjRS_n — DMA Resource Select Register n ............................................................. 676
7.3.24 DMAjBUFCR_n — DMA Buffer Control Register n .......................................................... 678
7.3.25 DMAjDPPTR_n — DMA Descriptor Pointer Register n.................................................... 679
7.3.26 DMAjDPCR_n — DMA Descriptor Control Register n...................................................... 680
7.3.27 Descriptor RAM — Descriptor Memory ............................................................................ 680
7.3.28 DMACSELj_m — sDMACj Transfer Request Group Selection Register m (m = 0 to 15) 681
7.4 Operation.................................................................................................................................... 683
7.4.1 DMA Transfer Requests................................................................................................... 683
7.4.2 DMA Interrupts ................................................................................................................. 688
7.4.3 Channel Priority................................................................................................................ 689
7.4.4 Slow Speed Mode ............................................................................................................ 690
7.4.5 Scatter Gather Transfer.................................................................................................... 690
7.4.6 Descriptors ....................................................................................................................... 694
7.4.7 Transfer Flow.................................................................................................................... 707
7.4.8 Performance..................................................................................................................... 709
Attn. Robert Bosch GmbH
7.5 Usage Notes............................................................................................................................... 710
7.6 Reliability Function...................................................................................................................... 714
7.6.1 Overview........................................................................................................................... 714
7.6.2 Master Information Inheritance Function.......................................................................... 714
7.7 Setting up DMA Transfer ............................................................................................................ 715
7.7.1 Overview of Setting up DMA Transfer.............................................................................. 715
7.7.2 Setting up the Transfer Request Group Selection............................................................ 715
7.7.3 Setting up the Overall DMA Operation ............................................................................. 715
7.7.4 Setting up the DMA Channel Setting................................................................................ 716
7.8 Related Requirements ............................................................................................................... 717
Section 8 DTS Controller ............................................................................................. 718
8.1 Features of DTS ......................................................................................................................... 718
8.1.1 Number of Units and Channels ........................................................................................ 718
8.1.2 Register Base Addresses................................................................................................. 718
8.1.3 Clock Supplies.................................................................................................................. 718
8.1.4 Interrupt Requests and Error Notifications ....................................................................... 719
8.1.5 DTS Transfer Requests.................................................................................................... 719
8.1.6 Reset Sources.................................................................................................................. 719
8.1.7 External Input/Output Signals........................................................................................... 719
8.2 Overview..................................................................................................................................... 720
8.2.1 Functional Overview......................................................................................................... 720
8.2.2 Definition of Terms ........................................................................................................... 721
8.3 Registers..................................................................................................................................... 722
8.3.1 List of Registers................................................................................................................ 722
8.3.2 Description of Global Registers........................................................................................ 723
8.3.3 Description of DTS Channel Registers............................................................................. 733
8.3.4 Detail DTSSELm .............................................................................................................. 752
8.4 Operation.................................................................................................................................... 754
8.4.1 Basic Operation of DTS Transfer ..................................................................................... 754
8.4.2 Channel Priority Order...................................................................................................... 758
8.4.3 Reload Function ............................................................................................................... 760
8.4.4 Chain Function ................................................................................................................. 764
8.4.5 DTS Operation.................................................................................................................. 766
8.5 Suspension, Resume, and Transfer Abort, and Clearing a DTS Transfer Request ................... 768
8.5.1 Suspend, Resume, and Transfer Abort of a DTS Transfer .............................................. 768
8.5.2 Masking and Clearing a Hardware DTS Transfer Request by DTSFSL........................... 769
8.5.3 List of Suspend, Resume, and Transfer Abort Functions................................................. 769
8.6 Error Control ............................................................................................................................... 770
8.6.1 Types of Errors................................................................................................................. 770
8.6.2 DTS Transfer Error........................................................................................................... 771
8.6.3 DTSRAM Error ................................................................................................................. 771
8.7 Reliability Function...................................................................................................................... 772
8.7.1 Overview........................................................................................................................... 772
Attn. Robert Bosch GmbH
8.7.2 Master Information Inheritance Function.......................................................................... 772
8.7.3 Restriction on Chain Function .......................................................................................... 773
8.8 Setting up DTS Transfer............................................................................................................. 773
8.8.1 Overview of Setting up DTS Transfer............................................................................... 773
8.8.2 Setting up the Transfer Request Group Selection............................................................ 774
8.8.3 Setting up the Overall DTS Operation.............................................................................. 774
8.8.4 Configuring the DTS Channel Settings............................................................................. 775
8.9 Related Requirements ............................................................................................................... 776
Section 9 Reset Controller........................................................................................... 777
9.1 Features...................................................................................................................................... 777
9.2 Input/Output Pins........................................................................................................................ 780
9.3 Interrupt Requests and Error Notifications.................................................................................. 780
9.4 Registers..................................................................................................................................... 781
9.4.1 List of Registers................................................................................................................ 781
9.4.2 Reset of Registers............................................................................................................ 784
9.4.3 STAC_DPRAM — RAM Initialization Mode Control Register for DPRAM ....................... 786
9.4.4 STAC_DTSRAM — RAM Initialization Mode Control Register for DTSRAM ................... 787
9.4.5 STAC_GTM — RAM Initialization Mode Control Register for GTM ................................ 788
9.4.6 STAC_MSPI — RAM Initialization Mode Control Register for MSPI................................ 789
9.4.7 STAC_MMCA — RAM Initialization Mode Control Register for MMCA ........................... 791
9.4.8 SWMRESA_RSCFD— Software Module Reset Assertion Register for RS-CANFD ....... 792
9.4.9 SWMRESS_RSCFD — Software Module Reset Status Register for RS-CANFD ........... 793
9.4.10 SWMRESA_FLXA — Software Module Reset Assertion Register for FLXA ................... 794
9.4.11 SWMRESS_FLXA — Software Module Reset Status Register for FLXA ........................ 795
9.4.12 SWMRESA_GTM — Software Module Reset Assertion Register for GTM ..................... 796
9.4.13 SWMRESS_GTM — Software Module Reset Status Register for GTM .......................... 797
9.4.14 SWMRESA_ETNB— Software Module Reset Assertion Register for ETNB ................... 798
9.4.15 SWMRESS_ETNB — Software Module Reset Status Register for ETNB....................... 799
9.4.16 SWMRESA_RSENT — Software Module Reset Assertion Register for RSENT............. 800
9.4.17 SWMRESS_RSENT — Software Module Reset Status Register for RSENT.................. 801
9.4.18 SWMRESA_MSPI — Software Module Reset Assertion Register for MSPI ................... 802
9.4.19 SWMRESS_MSPI — Software Module Reset Status Register for MSPI......................... 803
9.4.20 SWMRESA_RLIN3 — Software Module Reset Assertion Register for RLIN3 ................. 804
9.4.21 SWMRESS_RLIN3 — Software Module Reset Status Register for RLIN3...................... 806
9.4.22 SWMRESA_ADCJ_ISO — Software Module Reset Assertion Register for ADCJ (ISO). 808
9.4.23 SWMRESS_ADCJ_ISO — Software Module Reset Status Register for ADCJ (ISO)...... 809
9.4.24 SWMRESA_CXPI — Software Module Reset Assertion Register for CXPI..................... 810
9.4.25 SWMRESS_CXPI — Software Module Reset Status Register for CXPI ......................... 811
9.4.26 SWMRESA_MMCA — Software Module Reset Assertion Register for MMCA ............... 812
9.4.27 SWMRESS_MMCA — Software Module Reset Status Register for MMCA .................... 813
9.4.28 SWMRESA_ENCA — Software Module Reset Assertion Register for ENCA ................. 814
9.4.29 SWMRESS_ENCA — Software Module Reset Status Register for ENCA ...................... 815
9.4.30 SWMRESA_PSI5 — Software Module Reset
Assertion Register for
PSI5...................... 816
9.4.31 SWMRESS_PSI5 — Software Module Reset Status Register for PSI5........................... 817
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