642879 Intel Confidential 17
13.8.3.1 PM1_STS—Power Management 1 Status Register ........................ 512
13.8.3.2 PM1_EN—Power Management 1 Enable Register ......................... 515
13.8.3.3 PM1_CNT—Power Management 1 Control ................................... 516
13.8.3.4 PM1_TMR—Power Management 1 Timer Register......................... 517
13.8.3.5 PROC_CNT—Processor Control Register...................................... 517
13.8.3.6 LV2 — Level 2 Register............................................................ 519
13.8.3.7 LV3—Level 3 Register (Mobile Only) .......................................... 519
13.8.3.8 LV4—Level 4 Register (Mobile Only) .......................................... 519
13.8.3.9 LV5—Level 5 Register (Mobile Only) .......................................... 520
13.8.3.10LV6—Level 6 Register (Mobile Only) .......................................... 520
13.8.3.11GPE0_STS—General Purpose Event 0 Status Register .................. 521
13.8.3.12GPE0_EN—General Purpose Event 0 Enables Register .................. 524
13.8.3.13SMI_EN—SMI Control and Enable Register ................................. 526
13.8.3.14SMI_STS—SMI Status Register................................................. 528
13.8.3.15ALT_GP_SMI_EN—Alternate GPI SMI Enable Register .................. 531
13.8.3.16ALT_GP_SMI_STS—Alternate GPI SMI Status Register ................. 531
13.8.3.17UPRWC—USB Per-Port Registers Write Control............................ 532
13.8.3.18GPE_CNTL— General Purpose Control Register............................ 532
13.8.3.19DEVACT_STS — Device Activity Status Register .......................... 533
13.8.3.20PM2_CNT—Power Management 2 Control (Mobile Only)................ 534
13.8.3.21C3_RES— C3 Residency Register (Mobile Only)........................... 534
13.8.3.22C5_RES— C5 Residency Register (Mobile Only)........................... 535
13.9 System Management TCO Registers (D31:F0)..................................................... 536
13.9.1 TCO_RLD—TCO Timer Reload and Current Value Register.......................... 536
13.9.2 TCO_DAT_IN—TCO Data In Register....................................................... 537
13.9.3 TCO_DAT_OUT—TCO Data Out Register .................................................. 537
13.9.4 TCO1_STS—TCO1 Status Register .......................................................... 537
13.9.5 TCO2_STS—TCO2 Status Register .......................................................... 539
13.9.6 TCO1_CNT—TCO1 Control Register......................................................... 541
13.9.7 TCO2_CNT—TCO2 Control Register......................................................... 542
13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers....................................... 542
13.9.9 TCO_WDCNT—TCO Watchdog Control Register......................................... 543
13.9.10SW_IRQ_GEN—Software IRQ Generation Register .................................... 543
13.9.11TCO_TMR—TCO Timer Initial Value Register............................................. 543
13.10 General Purpose I/O Registers (D31:F0)............................................................. 544
13.10.1GPIO_USE_SEL—GPIO Use Select Register [31:0] .................................... 545
13.10.2GP_IO_SEL—GPIO Input/Output Select Register [31:0]............................. 545
13.10.3GP_LVL—GPIO Level for Input or Output Register [31:0]........................... 546
13.10.4GPO_BLINK—GPO Blink Enable Register [31:0] ........................................ 546
13.10.5GP_SER_BLINK[31:0]—GP Serial Blink [31:0].......................................... 547
13.10.6GP_SB_CMDSTS[31:0]—GP Serial Blink Command Status [31:0]................ 548
13.10.7GP_SB_DATA[31:0]—GP Serial Blink Data [31:0] ..................................... 548
13.10.8GPI_INV—GPIO Signal Invert Register [31:0]........................................... 549
13.10.9GPIO_USE_SEL2—GPIO Use Select 2 Register [60:32] .............................. 549
13.10.10GP_IO_SEL2—GPIO Input/Output Select 2 Register [60:32] ..................... 550
13.10.11GP_LVL2—GPIO Level for Input or Output 2 Register [63:32] ................... 550
14 SATA Controller Registers (D31:F2)....................................................................... 551
14.1 PCI Configuration Registers (SATA–D31:F2)........................................................ 551
14.1.1 VID—Vendor Identification Register (SATA—D31:F2) ................................ 552
14.1.2 DID—Device Identification Register (SATA—D31:F2)................................. 553
14.1.3 PCICMD—PCI Command Register (SATA–D31:F2)..................................... 553
14.1.4 PCISTS — PCI Status Register (SATA–D31:F2)......................................... 554
14.1.5 RID—Revision Identification Register (SATA—D31:F2)............................... 555
14.1.6 PI—Programming Interface Register (SATA–D31:F2)................................. 555
14.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h .......... 555
14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h .......... 556