NAU8810音频编解码芯片详细数据手册

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"NAU8810是NuVoton公司的一款高性能、低功耗、宽频带单声道音频编解码器（Codec），适用于各种音频应用，如语音电话。该芯片集成了5段图形均衡器、自动电平控制（ALC）带噪音门、可编程增益放大器（PGA）、标准I2S或PCM音频接口、可选PCM时隙分配以及全分数非片上锁相环（PLL）。" NAU8810的主要特性包括： 1. **差分/单声道音频编解码**：这款芯片提供了一种经济高效的方式来处理单声道音频信号，适合多种音频应用。 2. **2-wire Interface Control Interface**：通过两线制接口实现对芯片的控制，简化了系统设计，降低了布线复杂性。 3. **5-band Graphic Equalizer**：内置5段图形均衡器，允许用户调整音频频率响应，以优化不同音源的听感。 4. **Automatic Level Control (ALC) with Noise Gate**：ALC功能用于自动调节音频输出电平，防止过载，同时噪音门可以去除背景噪声。 5. **Programmable Gain Amplifier (PGA)**：PGA提供了从-12dB到+35.25dB的可编程增益，适应不同输入源的动态范围优化。 6. **Differential Microphone Input**：支持差分麦克风输入，提高了抗噪声能力，确保了高质量的音频输入。 7. **Variable Gain Control Stages**：音频路径中的多个可变增益控制阶段，可以灵活调整音频信号的大小。 8. **Digital Highpass Filter**：数字高通滤波器用于去除直流偏置电压，保持音频信号的清晰度。 9. **Voiceband Digital Filtering**：可编程的语音带数字过滤，优化了语音通信的质量。 10. **I2S and PCM Audio Interface**：支持多种I2S和PCM数据格式，兼容性强。 11. **PCM Timeslot Assignment**：可选的PCM时隙分配功能，方便在多通道系统中进行信号管理。 12. **Differential BTL Speaker Driver Output**：提供高功率的差分桥式负载（BTL）扬声器驱动输出，能驱动大功率的扬声器。在设计使用NAU8810的音频系统时，需要考虑这些特性，并根据实际需求配置芯片的各项参数，以实现最佳的音频性能和效率。此外，该芯片的全分数非片上PLL允许更精确的时钟管理和频率合成，进一步提高了音频质量。由于其低功耗特性，NAU8810尤其适合便携式和电池供电的设备。NAU8810是一款综合性的音频解决方案，能满足从基本的语音通话到复杂的音频处理应用的需求。

NAU8810

emPowerAudio

™

Datasheet Revision 2.8 Page 16 of 102 March 1, 2017

VDDD = 1.8V, VDDA = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), T

= +25

C, 1kHz signal, fs =

48kHz, 24-bit audio data unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Automatic Level Control (ALC)/Limiter – ADC only

Gain Ramp-Up (Decay) Time

DCY

ALC Mode

ALCM=0

MCLK=12.288MHz

3.3 / 6.6 / 13.1 / … /

3360 (time doubles every

step)

Limiter Mode

ALCM=1

MCLK=12.288MHz

0.73 / 1.45 / 2.91 / … /

744 (time doubles every

step)

Gain Ramp-Down (Attack)

Time

5, 6

ATK

ALC Mode

ALCM=0

MCLK=12.288MHz

0.83 / 1.66 / 3.33 / … /

852 (time doubles every

step)

Limiter Mode

ALCM=1

MCLK=12.288MHz

0.18 / 0.36 / 0.73 / … /

186 (time doubles every

step)

Digital Input / Output

Input HIGH Level

0.7 ×

VDDD

Input LOW Level

0.3 ×

VDDD

Output HIGH Level

= 1mA

0.9 ×

VDDD

Output LOW Level

= -1mA

0.1 x

VDDD

Notes

1. Full Scale is relative to VDDA (FS = VDDA/3.3.).

2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full-scale output and the

output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).

3. THD+N (dB) - THD+N are a ratio, of the RMS values, of (Noise + Distortion)/Signal.

4. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain.

It does not apply to ramping down the gain when the signal is too loud, which happens without a delay.

5. Ramp-up and Ramp-Down times are defined as the time to change the PGA gain by 6dB of its gain range.

6. All hold, ramp-up and ramp-down times scale proportionally with MCLK (specified for MCLK = 12.288MHz)

7. The maximum output voltage can be limited by the speaker power supply. If MOUTBST or SPKBST is, set

then VDDSPK should be 1.5xVDDA to prevent clipping taking place in the output stage (when PGA gains are set

to 0dB).

NAU8810

emPowerAudio

™

Datasheet Revision 2.8 Page 17 of 102 March 1, 2017

12. FUNCTIONAL DESCRIPTION

The NAU8810 a Mono Audio CODEC with very robust ADC and DAC capabilities. The device provides one

differential microphone input pair (MIC- & MIC+ pins) supported by a two-stage amplification path for amplification

by as much as 55.25dB. Additionally, the MIC+ pin can be used independently from the MIC- pin enabling two

independent mixing inputs for some applications.

The device also has an internal configurable biasing circuit for biasing the microphone, which reduces external

components. The PGA output has programmable ADC gain. An advanced Sigma Delta ADC and DAC are used

along with digital decimation and interpolation filters to give high quality audio at sample rates from 8 KHz to 48

KHz. The Digital Filter blocks include ADC high pass filters, a Notch Filter, and a 5-band equalizer. The device

has two output mixers, one for the Mono output, and the other for the speaker output.

The NAU88U10 has a 2-Wire read/write serial control interface for device control. Audio data is supported in

many commonly used industry formats as either I

S or PCM formatted data. Additionally, the PCM mode

supports time slotting for added design flexibility, such as in creation of multichannel systems using a shared

audio data bus.

The NAU88U10 can operate as a master or slave audio device. It can operate with sample rates ranging from 8

kHz to 48 kHz, depending on the values of MCLK and it is prescaler. The NAU88U10 includes a PLL block,

where it takes the external clock (MCLK pin) to generate other clocks for the audio data transfer such as Bit clock

(BCLK), Frame Sync (FS), and I

S clocks. The power control registers help save power by controlling the major

individual functional blocks of the NAU88U10.

12.1. INPUT PATH

The NAU88U10 microphone inputs are maintained at a DC bias at approximately a half of the VDDA supply

voltage. Connections to these inputs should be AC-coupled by means of DC blocking capacitors suitable for the

device application.

12.1.1. The differential microphone input (MIC- & MIC+ pins)

The NAU88U10 features a low-noise, high common mode rejection ratio (CMRR), differential microphone inputs

(MIC- & MIC+ pins) which are connected to a PGA Gain stage. The differential input structure is essential in

noisy digital systems where amplification of low-amplitude analog signals is required in products such as

notebooks and PDAs. When properly employed, the differential input architecture offers an improved power-

supply rejection ratio (PSRR) and higher ground noise immunity.

NAU8810

emPowerAudio

™

Datasheet Revision 2.8 Page 19 of 102 March 1, 2017

MIC+ to non-inverting PGA input

Nominal Input Impedance

MIC- to inverting PGA input

Nominal Input Impedance

Gain (dB)

Impedance (kΩ)

Gain (dB)

Impedance (kΩ)

-12

-9

-6

-3

2.9

35.25

1.6

Table 3: Microphone Non-Inverting

Input Impedances

Table 4: Microphone Inverting Input

Impedances

12.1.1.2. Negative Microphone Input (MIC-)

The negative microphone input (MIC-) may be used as either a differential input in conjunction with MIC+, or as a

single ended input. This input connects to the negative terminal of the PGA gain amplifier by setting NMICPGA[1]

address (0x2C) to HIGH. When the MIC- is used as a single ended input, MIC+ should be connected to VREF by

setting PMICPGA[0] address (0x2C) bit to LOW, or MIC+ may be used as an independent input.

When the associated control bit is set logic = 1, the MIC- pin is connected to a resistor of approximately 30kΩ

which is tied to VREF. The purpose of the tie to VREF is to reduce any pop or click sound by keeping the DC

level of the MIC- pin close to VREF at all times. It is important for a system designer to know that the MIC-input

impedance varies as a function of the selected PGA gain. This is normal and expected for a difference amplifier

type topology. The above table gives the nominal resistive impedance values for this input over the possible gain

range. Impedance for specific gain values not listed in this table can be estimated through interpolation between

listed values.

12.1.1.3. PGA Gain Control

The PGA amplification is common to both microphone input pins MIC-, MIC+, and enabled by PGAEN[2] address

(0x02). It has a range of -12dB to +35.25dB in 0.75dB steps, controlled by PGAGAIN[5:0] address (0x2D). Input

PGA gain will not be used when ALC is enabled using ALCEN[8] address (0x20).

Addr

Bit 8

Bit 7

Bit 6

Bit5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

0x2D

PGAZC

PGAMT

PGAGAIN[5:0]

0x010

0x20

ALCEN

ALCMXGAIN[2:0]

ALCMNGAIN[2:0]

0x038

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