瑞莎ISL94216：16-Cell电池管理前端芯片手册

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FN8936 Rev.3.00 Page 16 of 139

Sep 1, 2021

2. SpecificationsISL94216

ALRT (“ALRT Pin (40)” on page 93)

ALRT Pin Low Level Output Voltage ALRT

VOL

sink

= 2mA 0.2 0.4 V

ALRT

Sink Current ALRT

IOL

At 0.6V 4 mA

ALRT

Pin Leakage Current ALRT

LIH

-1 +1 µA

ALRT Pin Pulse Period ALRT

pulse_per

ALRT Pulse EN = 1 10 ms

ALRT

Pin On-Time ALRT

pulse_on

ALRT Pulse EN = 1 2 ms

WAKEUP

(“WAKEUP Pin (39)” on page 93)

WAKEUP Pin High Level Input Voltage WK

VIH

0.7xV

WAKEUP

Pin Low Level Input Voltage WK

VIL

0.3xV

WAKEUP

Pin Leakage Current WK

LIH

0V to 5.5V applied -1 +1 µA

WAKEUP

Low state pulse width WK

LPw

Minimum detectable pulse

width

100 ns

RESET

(“RESET Pin (38)” on page 92)

RESET Pin High Level Input Voltage RST

VIH

0.7xV

RESET

Pin Low Level Input Voltage RST

VIL

0.3xV

RESET

Pin Leakage Current High RST

LIH

0V to 5.5V applied -1 +1 µA

Power-On Reset Voltage at VBAT1

(Hysteresis 100mV Minimum)

POR

47V

Power-On Reset Startup Time to

Measurement

StartUp

BAT1

> V

POR

, RESET rising

edge or soft reset to first

measurement command

20 ms

Power-On Reset Communication

Lockout

RESET

BAT1

> V

POR

, RESET rising

edge or soft reset to first serial

communication command

activity (ACK)

200 µs

RESET

Low State Pulse Width RST

LPw

100 ns

SPI Interface Specifications (“SPI Serial Interface” on page 122)

Slave Address (7bits)

No CRC

SPI

Fixed 0001

010

Binary

Slave Address (7bits)

Use CRC

SPI

Fixed 1001

110

Binary

SCLK, MOSI, CS

Input Lo Voltage SPI_V

0.2xV

SCLK, MOSI, CS

Input Hi Voltage SPI_V

0.8xV

SCLK, MOSI, CS

Input Hysteresis SPI_V

HYS

0.05xV

SCLK, MOSI, CS

Input Current SPI_I

-1 +1 µA

SCLK, MOSI, CS Input Capacitance SPI_C

10 pF

MISO Output Lo Voltage SPI_V

2mA Sink Current 0 0.4 V

MISO Output Hi Voltage SPI_V

2mA Source Current V

-0.4V V

SCL Clock Frequency SPI_f

SCL

2MHz

Pulse Width of Input Spikes

Suppressed

SPI_t

IN1

Any pulse narrower than the

max spec is suppressed

50 ns

Clock High Time SPI_t

HIGH

200 ns

Clock Low Time SPI_t

LOW

200 ns

Unless otherwise specified: T

= +25°C, V

BAT1

= V

BAT2

= 48V, (VC

- VC

n-1

) = 3V, V

= V

= 3.3V, control registers at default,

= DGND = 0V, cell balancing is off. Voltages are with respect to V

. External components are per “Pin Functionality” on page 88.

(Continued)

Parameter Symbol Test Conditions

Min

(Note 10)

Typ

Max

(Note 10) Unit

FN8936 Rev.3.00 Page 17 of 139

Sep 1, 2021

2. SpecificationsISL94216

Enable Lag Time SPI_t

LAG

Last data read clock edge to

chip select high

250 ns

Time Delay Between Bytes SPI_t

WAIT

Time between falling edge of

the clock pulse corresponding

to the last bit of any byte, and

the next rising edge of the

clock corresponding to the first

bit of the next byte

7µs

Slave Access Time SPI_T

LEAD

Chip select low to SCLK rising

edge

200 ns

Data Valid Time SPI_t

Clock low to MISO valid 130 350 ns

Data Output Hold Time SPI_t

Data hold time after falling

edge of SCL

0 115 ns

MISO Disable Time SPI_t

DIS

MISO disabled following rising

edge of CS

240 ns

Data Setup Time SPI_t

Data input valid before rising

edge of SCL

100 ns

Data Input Hold Time SPI_t

Data input to remain valid

following rising edge of SCL

80 ns

MOSI Rise Time SPI_t

Up to 50pF load 30 ns

MOSI Fall Time SPI_t

Up to 50pF load 30 ns

C Interface Specifications (“I

C Serial Interface” on page 119)

Slave Address (7bits) SA

I2C

CS/Addr = VDD 0011

010

Binary

/Addr = DGND 0001

010

Binary

SDA and SCL Input Buffer LOW

Voltage

-0.3 0.3xV

SDA and SCL Input Buffer HIGH

Voltage

0.7xV

+0.3 V

SDA and SCL Input Buffer Hysteresis Hysteresis 0.05xV

SDA Output Buffer LOW Voltage V

Sinking 2mA 0 0.02 0.4 V

Pin Leakage Current for SDA and SCL

Pins

leak

-1 1 µA

SCL Frequency f

SCL

400 kHz

Pulse Width Suppression Time at SDA

and SCL Inputs

Any pulse narrower than the

Max value is suppressed

50 ns

SCL Falling Edge to SDA Output Data

Valid

SCL falling edge crossing 30%

of V

, until SDA exits the

30% to 70% of V

window

900 ns

Time the Bus Must be Free Before the

Start of a New Transmission

BUF

SDA crossing 70% of V

during a STOP condition, to

SDA crossing 70% of V

during the following START

condition

1300 ns

Clock LOW Time t

LOW

Measured at the 30% of V

crossing

1300 ns

Clock HIGH Time t

HIGH

Measured at the 70% of V

crossing

600 ns

Unless otherwise specified: T

= +25°C, V

BAT1

= V

BAT2

= 48V, (VC

- VC

n-1

) = 3V, V

= V

= 3.3V, control registers at default,

= DGND = 0V, cell balancing is off. Voltages are with respect to V

. External components are per “Pin Functionality” on page 88.

(Continued)

Parameter Symbol Test Conditions

Min

(Note 10)

Typ

Max

(Note 10) Unit

FN8936 Rev.3.00 Page 18 of 139

Sep 1, 2021

2. SpecificationsISL94216

Eighth Bit to ACK Bit Delay

(Applies to reading ADC Output Data

Only)

C_t

WAIT

Time between the rising edge

of the clock pulse

corresponding to the last bit of

any byte, and the falling edge

of the clock pulse

corresponding to the

Acknowledge bit

7µs

START Condition Setup Time t

SU:STA

SCL rising edge to SDA falling

edge. Both crossing 70% of

600 ns

START Condition Hold Time t

HD:STA

From SDA falling edge

crossing 30% of V

to SCL

falling edge crossing 70% of

600 ns

Input Data Setup Time t

SU:DAT

From SDA exiting the 30% to

70% of V

window, to SCL

rising edge crossing 30% of

100 ns

Input Data Hold Time t

HD:DAT

From SCL falling edge

crossing 30% of V

to SDA

entering the 30% to 70% of

window

20 900 ns

STOP Condition Setup Time t

SU:STO

From SCL rising edge

crossing 70% of V

, to SDA

rising edge crossing 30% of

600 17 ns

STOP Condition Hold Time t

HD:STO

From SDA rising edge to SCL

falling edge. Both crossing

70% of V

600 45 ns

Output Data Hold Time t

From SCL falling edge

crossing 30% of V

, until

SDA enters the 30% to 70% of

window

0 150 ns

SDA and SCL Rise Time t

From 30% to 70% of V

20+0.1xCb 300 ns

SDA and SCL Fall Time t

From 70% to 30% of V

20+0.1xCb 300 ns

Capacitive Loading of SDA or SCL Cb Total on-chip and off-chip 10 400 pF

SDA and SCL Bus Pull-Up Resistor

Off-Chip

Maximum is determined by t

and t

For Cb = 400pF, max is about

2kΩ~2.5kΩ

For Cb = 40pF, max is about

15kΩ~20kΩ

14.7 kΩ

Single Wire Interface Specifications (“

Single Wire Interface” on page 132) Notes 13, 14, and 15

Slave Address (7 bits) SA

CS/Addr = V

0011

010

Binary

/Addr = DGND 0001

010

Binary

Single Wire Input Low Voltage VSW

0.0 0.3xV

Single Wire Input High Voltage VSW

0.7xV

5.5 V

Output Buffer LOW Voltage V

= 2mA 0 0.02 0.4 V

Voltage Hysteresis V

hys

= 2mA 0.05 xV

Pin Leakage Current I

leak

1µA

Unless otherwise specified: T

= +25°C, V

BAT1

= V

BAT2

= 48V, (VC

- VC

n-1

) = 3V, V

= V

= 3.3V, control registers at default,

= DGND = 0V, cell balancing is off. Voltages are with respect to V

. External components are per “Pin Functionality” on page 88.

(Continued)

Parameter Symbol Test Conditions

Min

(Note 10)

Typ

Max

(Note 10) Unit

FN8936 Rev.3.00 Page 19 of 139

Sep 1, 2021

2. SpecificationsISL94216

Single Wire Pin Capacitance C

PINSW

10 pF

Capacitive Loading of Single Wire Cb

Total on-chip and off-chip 10 200 pF

Single Wire Bus Pull-Up Resistor

Off-Chip

PUSW

Max is determined by t

, t

and differences in master vs

slave IO Supply voltages (if

any)

14.7 kΩ

Rise Time t

rSW

30% to 70% of V

150 ns

Fall Time t

fSW

70% to 30% of V

150 ns

Time Out if the Voltage at Single Wire

stays LOW

TOLSW

300 µs

Time out if the Voltage at Single Wire

stays HIGH

TOHSW

35 ms

Glitch Filtering t

glitch

Pulses narrower than Min are

ignored

50 ns

Transmitter Single Wire Timing Specifications

Hold Low Time t

HLDSW

The time the line is held low by

the master after a falling edge

2µs

Pulse-Width of Not Present (NACK),

Read 1, or Write 1

1NPresSW

23µs

Pulse-Width of Present (ACK), Read 0,

or Write 0

0PresSW

57.6µs

Pulse-Width of Reset (Start) t

RstSW

100 150 µs

Falling edge of a 1 or Not Present to

next symbol’s falling edge

1BPSW

5µs

Falling edge of a 0 or Present to next

symbol’s falling edge

0BPSW

12 µs

Pulse-Width of Load (Stop) t

LdSW

12 18

Falling edge of a Load to next symbol’s

falling edge

LdBPSW

40 µs

Falling edge of a Reset to next

symbol’s falling edge

RstBPSW

250 µs

Time out if the Voltage at Single Wire

stays LOW

TOLSW

300 µs

Time out if the Voltage at Single Wire

stays HIGH

TOHSW

40 ms

Receiver Single Wire Timing Specifications

Narrow Pulse-Width Threshold for Not

Present (NACK) or “1”

DetNSW

1.0 1.8 µs

Wide Pulse-Width Threshold for Not

Present (NACK) or “1”, and Narrow

Pulse-Width Threshold for Present

(ACK) or “0”

DetWSW

3.2 4.8 µs

Wide Pulse-Width Threshold for

Present (ACK) or “0”, and Narrow

Pulse-Width Threshold for Load (Stop)

Det0LdSW

7.8 11.8 µs

Wide Pulse-Width Threshold for Load

(Stop), and Narrow Pulse-Width

Threshold for Reset (Start)

DetLdRstSW

20 30 µs

Unless otherwise specified: T

= +25°C, V

BAT1

= V

BAT2

= 48V, (VC

- VC

n-1

) = 3V, V

= V

= 3.3V, control registers at default,

= DGND = 0V, cell balancing is off. Voltages are with respect to V

. External components are per “Pin Functionality” on page 88.

(Continued)

Parameter Symbol Test Conditions

Min

(Note 10)

Typ

Max

(Note 10) Unit

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