Chin. Phys. B Vol. 22, No. 1 (2013) 018501
A simple and accurate method for measuring program/erase
speed in a memory capacitor structure
∗
Jin Lin(7 )
a)b)
, Zhang Man-Hong(Ü÷ù)
a)
, Huo Zong-Liang(¿m)
a)
, Wang Yong( [)
a)
,
Yu Zhao-An({îS)
a)
, Jiang Dan-Dan(ñûû)
a)b)
, Chen Jun-Ning(•w)
b)
, and Liu Ming(4 ²)
a)†
a)
Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
b)
School of Electronics and Information Engineering, Anhui University, Hefei 230039, China
(Received 15 April 2012; revised manuscript received 21 June 2012)
With the merits of a simple process and a short fabrication period, the capacitor structure provides a convenient
way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a
capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor
is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can
be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively
characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this
time constant is greatly reduced and the measured minority carrier-related program/erase speed is in agreement with the
reported value in a transistor structure.
Keywords: memory capacitor, program/erase speed, minority carrier generation, illumination
PACS: 85.30.–z DOI: 10.1088/1674-1056/22/1/018501
1. Introduction
Owing to the advantages of low power consump-
tion, multi-bit storage, and potential applications in three-
dimensional (3D) integration, the charge trap memory (CTM)
has attracted extensive attention in both the academic and the
industrial fields.
[1,2]
Currently, a lot of effort has been made
to evaluate the CTM gate stacks with various materials and
architectures.
[3,4]
With the merits of a simple process and a
short fabrication period, the capacitor structure provides a con-
venient way to evaluate memory characteristics such as pro-
gram/erase (P/E) speed, data retention and endurance. Dif-
ferent from the transistor structures in which the source and
drain can provide minority carriers to the channel, the capac-
itor structures may have a very long formation time of the
inversion layer due to the very slow thermal generation pro-
cess for minority carriers.
[5]
During a fast program for an n-
channel capacitor (or a fast erase for a p-channel one), the mi-
nority carrier generation may not be able to follow the gate
bias pulse, which results in an inaccurate measurement of mi-
nority carrier-related P/E speed in the memory capacitor struc-
ture.
In this paper, we propose a simple and accurate method
for measuring the P/E speed in the memory capacitor struc-
ture using light illumination. It includes the characterization
of light intensity dependent formation time of the inversion
layer and the comparison between the minority carrier-related
P/E speed under high light illumination and literature reported
values in transistor structures.
2. Effect of slow minority carrier generation
time in memory capacitors
Following the conventional notation in this paper we re-
fer to capacitors on p- and n-type Si substrates as n- and p-
channel capacitors, respectively. In the inversion regime, the
P/E operation of the memory capacitor depends on both the
electric field in the tunneling layer and the density of minority
carriers.
[6]
Due to the slow generation rate of minority carriers,
the memory capacitor may enter into a non-equilibrium state.
In such a state the voltage drops across the gate stack and the
Si substrate are different from those in a thermal equilibrium
state. Thus the P/E transients are also different. As an ex-
ample, we calculate the voltage drop V
ox
across the gate stack
versus the substrate donor doping in a p-channel capacitor un-
der the thermal equilibrium and the deep depletion conditions.
In the calculation, it is assumed that there are no inversion
carriers so that the capacitor is in the deep depletion condi-
tion (the fully non-equilibrium case).
[7]
The equivalent oxide
thickness (EOT) of the capacitor is taken to be 15 nm, and the
work function of the Al gate electrode is adopted as 4.08 eV.
The gate bias is fixed at V
g
= −15 V. Figure 1 shows the re-
sults of such a model calculation. It can be seen that under the
deep depletion condition, most of the gate bias drops across
∗
Project supported by the National Basic Research Program of China (Grant Nos. 2010CB934200 and 2011CBA00600), the National Natural Science Foundation
of China (Grant Nos. 7360825403, 61176080, and 61176073), and the National Science and Technology Major Project of China (Grant No. 2009ZX02023-
005).
†
Corresponding author. E-mail: liuming@ime.ac.cn
© 2013 Chinese Physical Society and IOP Publishing Ltd http://iopscience.iop.org/cpb http://cpb.iphy.ac.cn
018501-1
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