Tables
xviiContents
7−22 Register Bits Used to Set the SRG Frame-Sync Period and Pulse Width 7-29. . . . . . . . . . . .
7−23 Register Bits Used to Set the Receive Clock Mode 7-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−24 Select Sources to Provide the Receive Clock Signal and the Effect on the
CLKR Pin 7-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−25 Register Bit Used to Set Receive Clock Polarity 7-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−26 Register Bits Used to Set the Sample Rate Generator (SRG) Clock
Divide-Down Value 7-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−27 Register Bit Used to Set the SRG Clock Synchronization Mode 7-39. . . . . . . . . . . . . . . . . . . .
7−28 Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock) 7-40. . . . . . . . . . . .
7−29 Register Bits Used to Set the SRG Input Clock Polarity 7-41. . . . . . . . . . . . . . . . . . . . . . . . . . .
8−1 Register Bits Used to Place Transmitter in Reset 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−2 Reset State of Each McBSP Pin 8-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−3 Register Bit Used to Set Transmitter Pins to Operate as McBSP Pins 8-6. . . . . . . . . . . . . . . .
8−4 Register Bit Used to Enable/Disable the Digital Loopback Mode 8-7. . . . . . . . . . . . . . . . . . . . .
8−5 Receive Signals Connected to Transmit Signals in Digital Loopback Mode 8-7. . . . . . . . . . . .
8−6 Register Bits Used to Enable/Disable the Clock Stop Mode 8-8. . . . . . . . . . . . . . . . . . . . . . . . .
8−7 Register Bits Used to Enable/Disable Transmit Multichannel Selection 8-9. . . . . . . . . . . . . . .
8−8 Register Bit Used to Choose One or Two Phases for the Transmit Frame 8-10. . . . . . . . . . . .
8−9 Register Bits Used to Set the Transmit Word Length(s) 8-11. . . . . . . . . . . . . . . . . . . . . . . . . . .
8−10 Register Bits Used to Set the Transmit Frame Length 8-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−11 How to Calculate Frame Length 8-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−12 Register Bit Used to Enable/Disable the Transmit Frame-Sync Ignore Function 8-15. . . . . .
8−13 Register Bits Used to Set the Transmit Companding Mode 8-16. . . . . . . . . . . . . . . . . . . . . . . .
8−14 Register Bits Used to Set the Transmit Data Delay 8-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−15 Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode 8-20. . . . . . . . . . . .
8−16 Register Bits Used to Set the Transmit Interrupt Mode 8-21. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
−17 Register Bits Used to Set the Transmit Frame-Sync Mode 8-22. . . . . . . . . . . . . . . . . . . . . . . . .
8−18 How FSXM and FSGM Select the Source of Transmit Frame-Sync Pulses 8-23. . . . . . . . . . .
8−19 Register Bit Used to Set Transmit Frame-Sync Polarity 8-24. . . . . . . . . . . . . . . . . . . . . . . . . . .
8−20 Register Bits Used to Set the SRG Frame-Sync Period and Pulse Width 8-27. . . . . . . . . . . .
8−21 Register Bit Used to Set the Transmit Clock Mode 8-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−22 How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status
of the CLKX Pin 8-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−23 Register Bit Used to Set Transmit Clock Polarity 8-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−24 Register Bits Used to Set the Sample Rate Generator (SRG) Clock
Divide-Down Value 8-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−25 Register Bit Used to Set the SRG Clock Synchronization Mode 8-36. . . . . . . . . . . . . . . . . . . .
8−26 Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock) 8-37. . . . . . . . . . . .
8−27 Register Bits Used to Set the SRG Input Clock Polarity 8-38. . . . . . . . . . . . . . . . . . . . . . . . . . .
9−1 How To Use McBSP Pins for General-Purpose I/O 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10−1 McBSP Emulation Modes Selectable With the FREE and SOFT Bits of SPCR2 10-2. . . . . .
10−2 Reset State of Each McBSP Pin 10-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12−1 SPCR1 Bit Descriptions 12-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12−2 SPCR2 Bit Descriptions 12-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12−3 RCR1 BIt Descriptions 12-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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