ARM平台硬件加速：NEON指令详解

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"《CodingForNeon》是关于ARM平台上的NEON指令集的使用指南，专注于通过NEON指令实现硬件加速，特别是SIMD（单指令多数据）技术，以提高寄存器并行运算的效率。文档经过多次更新，增加了矩阵乘法、移位操作等章节，旨在帮助开发者充分利用NEON指令提升计算性能。" NEON指令集是ARM架构中的一种高级 SIMD（Single Instruction Multiple Data）向量处理单元，设计用于加速媒体处理、图像处理和信号处理等计算密集型任务。NEON是ARMv7-A及更高版本架构的一部分，并在ARM Cortex-A 系列处理器中广泛使用。它提供了并行处理能力，能够在单个周期内执行多个数据元素的操作，显著提高了执行效率。 1. SIMD技术：SIMD允许同一指令同时处理多个数据，对于处理数组和矩阵等大规模数据操作特别有效。例如，在视频编码和解码、图像缩放、音频处理等领域，可以同时处理多个像素或样本，大大减少了计算时间。 2. NEON寄存器：NEON拥有自己的专用寄存器集，这些寄存器比通用CPU寄存器更宽，可以存储更多的数据。它们可以并行处理多个单精度浮点数或者整数，增强了处理速度。 3. 矩阵乘法：NEON指令集支持高效的矩阵运算，这对于机器学习、计算机视觉和游戏开发等领域的算法至关重要。通过特定的向量操作，可以快速执行矩阵乘法，减少计算延迟。 4. 移位操作：文档的第四版中新增了移位操作的章节，移位操作是计算机编程中一种重要的位操作，可以用来高效地调整数值的二进制位位置，这在处理位掩码、数据打包和解包等场景中非常有用。 5. 加载与存储左移：文档的早期版本中介绍了如何有效地处理加载和存储过程中剩余的数据，这对于内存优化和避免数据溢出非常重要。 6. 排列指令：NEON还提供了一系列指令用于数据的重新排列，比如将数据在向量内的位置进行交换或移动，这对于处理交错数据或执行特定数据变换时很有帮助。 7. 版权与使用许可：该文档受到版权保护，并且可能涉及专利，未经ARM有限公司的明确书面许可，不得复制或使用其中的信息。通过理解和熟练运用《CodingForNeon》中的知识，开发者能够编写出更高效、更优化的代码，充分发挥ARM平台上NEON指令集的硬件加速潜力，提升应用程序的运行速度和性能。

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The following diagram shows how the above instruction separates the different data channels:

The red and blue values can now be switched easily using the MOV instruction to copy the entire

vector. Finally, we write the data back to memory, with reinterleaving, using the ST3 store

instruction.

A single iteration of this RGB to BGR switch can be coded as follows:

LD3 { V0.16B, V1.16B, V2.16B }, [x0], #48 // 3-way interleaved load from

// address in X0, post-incremented

// by 48

MOV V3.16B, V0.16B // Swap V0 -> V3

MOV V0.16B, V2.16B // Swap V2 -> V0

MOV V2.16B, V3.16B // Swap V3 -> V2

// (net effect is to swap V0 and V2)

ST3 { V0.16B, V1.16B, V2.16B }, [x1], #48 // 3-way interleaved store to address

// in X1, post-incremented by 48

Each iteration of this code does the following:

• Loads from memory 16 red bytes into V0, 16 green bytes into V1, and 16 blue bytes into V2.

• Increments the source pointer in X0 by 48 bytes ready for the next iteration. The increment of 48

bytes is the total number of bytes that we read into all three registers, so 3 x 16 bytes in total.

• Swaps the vector of red values in V0 with the vector of blue values in V2, using V3 as an

intermediary.

• Stores the data in V0, V1, and V2 to memory, starting at the address that is specified by the

destination pointer in X1, and increments the pointer.

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• A set of 64-bit Neon registers to be read or written. A maximum of four registers can be listed,

depending on the interleave pattern. Each entry in the set of Neon registers has two parts:

o The Neon register name, for example V0.

o An arrangement specifier. This indicates the number of bits in each element and the number

of elements that can fit in the Neon vector register. For example, 16B indicates that each

element is one byte (B), and each vector is a 128-bit vector containing 16 elements.

• A general-purpose register containing the location to access in memory. The address can be

updated after the access.

3.2 Interleave pattern

Neon provides instructions to load and store interleaved structures containing from one to four

equally sized elements. Elements are the standard Neon-supported widths of 8 (B), 16 (H), 32 (S), or

64 (D) bits.

• LD1 is the simplest form. It loads one to four registers of data from memory, with no

deinterleaving. You can use LD1 to process an array of non-interleaved data.

• LD2 loads two or four registers of data, deinterleaving even and odd elements into those

registers. You can use LD2 to separate stereo audio data into left and right channels.

• LD3 loads three registers and deinterleaves. You can use LD3 to split RGB pixel data into

separate color channels.

• LD4 loads four registers and deinterleaves. You can use LD4 to process ARGB image data.

The store instructions ST1, ST2, ST3, and ST4 support the same options, but interleave the data

from registers before writing them to memory.

3.3 Element types

Loads and stores interleave elements based on the size that is specified to the instruction.

For example, consider the following instruction:

LD2 {V0.8H, V1.8H}, [X0]

This instruction loads two Neon registers with deinterleaved data starting from the memory address

in X0. The 8H in the arrangement specifier indicates that each element is a 16-bit halfword (H), and

each Neon register is loaded with eight elements. This instruction therefore results in eight 16-bit

elements in the first register V0, and eight 16-bit elements in the second register V1. Adjacent pairs

(even and odd) are separated to each register, as shown in the following diagram:

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ARM平台硬件加速：NEON指令详解

NEON-intrinsics.pdf

ARM NEON 使用手册

neon programmers guide

codeblocks中无法inculude arm_neon.h

linux下arm_neon.h文件在那个路径下

介绍一下<arm_neon.h>头文件

arm_neon.h有哪些功能

如何手动安装包含`arm_neon.h`的库？

#include<arm_neon.h>、

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