EZ-USB FX3™ USB3.0硬件设计与调试指南

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"USB3.0芯片cyusb3014硬件设计指南是 Cypress 官方文档，由Rizwan Afridi和Hussein Osman撰写，涵盖了EZ-USB FX3系列，特别是CYUSB3014芯片的硬件设计推荐实践和关键注意事项。文档详细讨论了电源系统、时钟配置、接口设计、低功耗外设、启动过程以及电磁干扰（EMI）和静电放电（ESD）考虑等关键主题，旨在帮助开发者实现高效的USB3.0外设控制器设计。" 本文档首先介绍了EZ-USB FX3芯片，它是一款高度集成且灵活的USB3.0外围控制器，可以方便地为各种系统添加USB3.0功能。接下来，详细讲述了以下几个方面： 1. **电源系统**：包括概述、电源模式、设备供应去耦合、浪涌电流考虑及电源供应设计。电源系统的设计至关重要，因为它直接影响到设备的稳定性和性能。 2. **时钟配置**：涉及到晶体、时钟和看门狗定时器。正确的时钟配置是确保数据传输准确性和系统稳定性的重要因素。 3. **GPIFII接口**：通用并行接口II，是FX3芯片与外部硬件进行高速数据交换的关键接口。 4. **I2C接口**：一种低速通信协议，用于设备间的简单通信。 5. **低功耗外设**：如JTAG、I2S、SPI和UART，这些接口在低功耗应用中非常有用。 6. **启动过程**：详述了设备的启动流程，这对于理解设备如何开始工作和如何正确配置至关重要。 7. **EMI和ESD考虑**：设计者必须考虑到设备的电磁兼容性和静电防护措施，以满足法规要求并确保设备的可靠性。 8. **FX3设备封装尺寸**：提供了芯片的实际尺寸信息，对于PCB布局有直接影响。 9. **电气设计考虑**：特别提到了USB3.0超速设计指南，这是实现高速USB连接的关键。 10. **附录A - PCB布局技巧**：提供了一些实用的印刷电路板布局建议，以优化信号完整性和减少潜在问题。总体来说，"USB3.0芯片cyusb3014硬件设计指南"为开发者提供了一份全面的参考，从硬件设计的基础到高级技巧，涵盖了一系列设计和实施USB3.0解决方案所需的知识点。

EZ-USB

FX3™ Hardware Design Guidelines and Schematic Checklist

www.cypress.com Document No. 001-70707 Rev. *E 4

Inrush Current Consideration and Power

Supply Design

When the USB 3.0 Super Speed PHY is enabled for the

first time, or a reset event; an initial inrush current is

expected on the 1.2 V U3RXVDDQ and U3TXVDDQ

supplies for ~10 us. The magnitude of this current can be

as high as 800 mA. In order that this inrush current does

not cause the common 1.2 V supply to droop to

unacceptable levels, care must be taken in the design of

the power supply network for these supplies.

If the same 1.2 V supply is also used for the VDD core

supply, care must be taken to insure that the level on this

supply does not fall too low, as this has the potential to trip

the on-chip power-on reset (POR) circuit that will reset the

entire chip. The POR circuit can fire if the 1.2-V core VDD

voltage falls down to less than 0.83 V for more than

200 ns. The 1.2-V power network must be designed such

that the VDD does not drop below 0.83 V when an inrush

event occurs. Proper combination of decoupling capacitors

(as specified in the datasheet), inductor chokes and

regulator output impedance are required to make this

possible.

The following example waveforms show the inrush current

(Figure 4) and resultant drop in VDD levels (Figure 5)

when the current spike occurs. The results were obtained

from a non-optimized power supply design using

TPS76801QD power regulator, 2.2-uF decoupling caps,

and chokes as shown in Figure 3.

Figure 3. Non-optimized Power Supply Design

U3RXVDDQ

U3TXVDDQ

VDD

FX3

0.1µF 2.2µF

Lchoke

Regulator

TPS76801QD

V1P2

Figure 4. Inrush Current (80 mV/0.1 Ω = 800 mA)

Figure 5. 1.2-V Power Domain Voltage Drop (200 mV)

In contrast, an optimized power design shown in Figure 6

below designed using the same regulator (TPS76801QD),

with the modification of using a 22-uF decoupling

capacitor and removing the choke from VDD supply,

shows a reduction in the inrush (Figure 7) and an

improvement in the power supply drop (Figure 8).

Figure 6. Optimized Power Supply Design

U3RXVDDQ

U3TXVDDQ

VDD

FX3

0.1µF 22µF

Lchoke

Regulator

TPS76801QD

V1P2

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