Intel 64 and IA-32 Architectures System Programming Guide

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"Intel 64 and IA-32 Architectures Software Developer's Manual volume 3B" 《Intel 64 and IA-32 Architectures Software Developer's Manual》是Intel公司为软件开发者提供的一份详尽的技术指南，旨在帮助开发者理解和利用Intel 64（也称为x86-64）和IA-32架构进行系统编程。该手册由五个卷组成，覆盖了从基础架构到指令集参考再到系统编程的各个方面。 Volume 3B：System Programming Guide, Part 2 是手册的第二部分，主要关注更深入的系统编程主题。这包括但不限于以下关键知识点： 1. **内存管理**：这部分详细介绍了Intel 64和IA-32架构中的内存模型，包括分页机制、页表结构、地址空间布局以及如何在多级分页系统中管理虚拟内存。 2. **中断和异常处理**：涵盖了中断、异常的分类、处理流程、中断向量表（IDT）和中断描述符（Interrupt Descriptors）的结构，以及中断和异常的上下文切换。 3. **处理器状态和特权级别**：讲解了不同特权级别的概念，如Ring 0（操作系统内核）和Ring 3（用户程序），以及如何在这些级别之间切换。 4. **系统调用和异常处理**：描述了如何通过中断机制实现系统调用，以及系统调用接口的规范和实现。 5. **设备驱动程序编程**：涵盖了与硬件设备交互的基本原理，包括I/O端口、中断控制、DMA（直接存储器访问）以及中断控制器的操作。 6. **同步和互斥机制**：讨论了锁、信号量、事件对象等同步原语，以及多处理器系统下的线程安全问题。 7. **性能监控和事件计数器**：介绍了CPU内置的性能监控功能，如PMC（Performance Monitoring Counters），以及如何使用它们来优化代码。 8. **虚拟化技术**：详细阐述了Intel VT-x（虚拟化技术扩展）和EPT（扩展页表）等特性，以及如何在硬件层面支持虚拟机。 9. **电源管理和ACPI**：涉及CPU的低功耗模式，如C状态（C1到C6），以及Advanced Configuration and Power Interface（ACPI）规范，用于系统的电源管理。 10. **线程和进程管理**：解释了操作系统的线程和进程模型，包括调度策略、上下文切换以及线程间的通信机制。该手册的目的是确保开发者能够充分利用Intel处理器提供的功能，同时遵循最佳实践，以实现高效、稳定和安全的软件。由于其内容广泛且深入，它是开发针对Intel平台的系统级软件和驱动程序的宝贵参考资料。对于任何想要深入理解Intel处理器工作原理的开发者来说，这是一本不可或缺的读物。

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21-8 Vol. 3

VIRTUAL-MACHINE CONTROL STRUCTURES

—2: Shutdown. The logical processor is inactive because it incurred a triple

fault

or some other serious error.

—3: Wait-for-SIPI. The logical processor is inactive because it is waiting for a

startup-IPI (SIPI).

Future processors may include support for other activity states. Software should

read the VMX capability MSR IA32_VMX_MISC (see Appendix G.6) to determine

what activity states are supported.

• Interruptibility state (32 bits). The IA-32 architecture includes features that

permit certain events to be blocked for a period of time. This field contains

information about such blocking. Details and the format of this field are given in

Table 21-3.

1. A triple fault occurs when a logical processor encounters an exception while attempting to

deliver a double fault.

Table 21-3. Format of Interruptibility State

Bit

Position(s)

Bit Name Notes

0 Blocking by STI See the “STI—Set Interrupt Flag” section in Chapter 4 of the

Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 2B.

Execution of STI with RFLAGS.IF = 0 blocks interrupts (and,

optionally, other events) for one instruction after its

execution. Setting this bit indicates that this blocking is in

effect.

1Blocking by

MOV SS

See the “MOV—Move a Value from the Stack” and “POP—Pop

a Value from the Stack” sections in Chapter 3 and Chapter 4

of the Intel® 64 and IA-32 Architectures Software

Developer’s Manual, Volumes 2A & 2B, and Section 6.8.3 in

the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 3A.

Execution of a MOV to SS or a POP to SS blocks interrupts for

one instruction after its execution. In addition, certain debug

exceptions are inhibited between a MOV to SS or a POP to SS

and a subsequent instruction. Setting this bit indicates that

the blocking of all these events is in effect. This document

uses the term “blocking by MOV SS,” but it applies equally to

POP SS.

2 Blocking by SMI See Section 26.2. System-management interrupts (SMIs) are

disabled while the processor is in system-management mode

(SMM). Setting this bit indicates that blocking of SMIs is in

effect.

Vol. 3 21-9

VIRTUAL-MACHINE CONTROL STRUCTURES

• Pending debug exceptions (64 bits; 32 bits on processors that do not support

Intel 64 architecture). IA-32 processors may recognize one or more debug

exceptions without immediately delivering them.

This field contains information

about such exceptions. This field is described in Table 21-4.

3 Blocking by NMI See Section 6.7.1 in the Intel® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 3A and Section 26.8.

Delivery of a non-maskable interrupt (NMI) or a system-

management interrupt (SMI) blocks subsequent NMIs until

the next execution of IRET. See Section 22.4 for how this

behavior of IRET may change in VMX non-root operation.

Setting this bit indicates that blocking of NMIs is in effect.

Clearing this bit does not imply that NMIs are not

(temporarily) blocked for other reasons.

If the “virtual NMIs” VM-execution control (see Section

21.6.1) is 1, this bit does not control the blocking of NMIs.

Instead, it refers to “virtual-NMI blocking” (the fact that guest

software is not ready for an NMI).

31:4 Reserved VM entry will fail if these bits are not 0. See Section 23.3.1.5.

1. For example, execution of a MOV to SS or a POP to SS may inhibit some debug exceptions for one

instruction. See Section 6.8.3 of Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 3A. In addition, certain events incident to an instruction (for example, an INIT signal) may

take priority over debug traps generated by that instruction. See Table 6-2 in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Table 21-4. Format of Pending-Debug-Exceptions

Bit

Position(s)

Bit Name Notes

3:0 B3 – B0 When set, each of these bits indicates that the corresponding

breakpoint condition was met. Any of these bits may be set

even if the corresponding enabling bit in DR7 is not set.

11:4 Reserved VM entry fails if these bits are not 0. See Section 23.3.1.5.

12 Enabled

breakpoint

When set, this bit indicates that at least one data or I/O

breakpoint was met and was enabled in DR7.

Table 21-3. Format of Interruptibility State (Contd.)

Bit

Position(s)

Bit Name Notes

21-10 Vol. 3

VIRTUAL-MACHINE CONTROL STRUCTURES

• VMCS link pointer (64 bits). This field is included for future expansion. Software

should set this field to FFFFFFFF_FFFFFFFFH to avoid VM-entry failures (see

Section 23.3.1.5).

• VMX-preemption timer value (32 bits). This field is supported only on logical

processors that support the 1-setting of the “activate VMX-preemption timer”

VM-execution control. This field contains the value that the VMX-preemption

timer will use following the next VM entry with that setting. See Section 22.7.1

and Section 23.6.4.

• Page-directory-pointer-table entries (PDPTEs; 64 bits each). These four (4)

fields (PDPTE0, PDPTE1, PDPTE2, and PDPTE3) are supported only on logical

processors that support the 1-setting of the “enable EPT” VM-execution control.

They correspond to the PDPTEs referenced by CR3 when PAE paging is in use (see

Section 4.4 in the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 3A). They are used only if the “enable EPT” VM-execution control

is 1.

21.5 HOST-STATE AREA

This section describes fields contained in the host-state area of the VMCS. As noted

earlier, processor state is loaded from these fields on every VM exit (see Section

24.5).

All fields in the host-state area correspond to processor registers:

• CR0, CR3, and CR4 (64 bits each; 32 bits on processors that do not support Intel

64 architecture).

• RSP and RIP (64 bits each; 32 bits on processors that do not support Intel 64

architecture).

• Selector fields (16 bits each) for the segment registers CS, SS, DS, ES, FS, GS,

and TR. There is no field in the host-state area for the LDTR selector.

• Base-address fields for FS, GS, TR, GDTR, and IDTR (64 bits each; 32 bits on

processors that do not support Intel 64 architecture).

13 Reserved VM entry fails if this bit is not 0. See Section 23.3.1.5.

14 BS When set, this bit indicates that a debug exception would

have been triggered by single-step execution mode.

63:15 Reserved VM entry fails if these bits are not 0. See Section 23.3.1.5.

Bits 63:32 exist only on processors that support Intel 64

architecture.

Table 21-4. Format of Pending-Debug-Exceptions (Contd.)

Bit

Position(s)

Bit Name Notes

21-12 Vol. 3

VIRTUAL-MACHINE CONTROL STRUCTURES

All other bits in this field are reserved, some to 0 and some to 1. Software should

consult the VMX capability MSRs IA32_VMX_PINBASED_CTLS and

IA32_VMX_TRUE_PINBASED_CTLS (see Appendix G.3.1) to determine how to set

reserved bits. Failure to set reserved bits properly causes subsequent VM entries to

fail (see Section 23.2).

The first processors to support the virtual-machine extensions supported only the 1-

settings of bits 1, 2, and 4. The VMX capability MSR IA32_VMX_PINBASED_CTLS will

always report that these bits must be 1. Logical processors that support the 0-

settings of any of these bits will support the VMX capability MSR

IA32_VMX_TRUE_PINBASED_CTLS MSR, and software should consult this MSR to

discover support for the 0-settings of these bits. Software that is not aware of the

functionality of any one of these bits should set that bit to 1.

21.6.2 Processor-Based VM-Execution Controls

The processor-based VM-execution controls constitute two 32-bit vectors that

govern the handling of synchronous events, mainly those caused by the execution of

specific instructions.

These are the primary processor-based VM-execution

controls and the secondary processor-based VM-execution controls.

Table 21-5. Definitions of Pin-Based VM-Execution Controls

Bit Position(s) Name Description

0External-interrupt

exiting

If this control is 1, external interrupts cause VM exits.

Otherwise, they are delivered normally through the guest

interrupt-descriptor table (IDT). If this control is 1, the value

of RFLAGS.IF does not affect interrupt blocking.

3 NMI exiting If this control is 1, non-maskable interrupts (NMIs) cause

VM exits. Otherwise, they are delivered normally using

descriptor 2 of the IDT. This control also determines

interactions between IRET and blocking by NMI (see Section

22.4).

5 Virtual NMIs If this control is 1, NMIs are never blocked and the “blocking

by NMI” bit (bit 3) in the interruptibility-state field indicates

“virtual-NMI blocking” (see Table 21-3). This control also

interacts with the “NMI-window exiting” VM-execution

control (see Section 21.6.2).

This control can be set only if the “NMI exiting” VM-execution

control (above) is 1.

6Activate VMX-

preemption timer

If this control is 1, the VMX-preemption timer counts down in

VMX non-root operation; see Section 22.7.1. A VM exit occurs

when the timer counts down to zero; see Section 22.3.

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