Lattice ECP3 DDR3 Demo User Guide: Configuration and Demonstrati...
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本指南是针对Lattice ECP3 Versa Evaluation Board（LEVB）用户的DDR3 Demo设计手册，发布于2011年5月。该文档旨在提供关于如何利用Lattice半导体的ECP3 DDR3 IP核心在LEVB上实现400MHz速度下800Mbps操作的技术细节和步骤。Lattice ECP3 Versa Development Kit随附了LEVB、USB线、电源供应以及演示文件，全面支持这一演示设计。
演示设计的重点在于展示ECP3芯片对DDR3 SDRAM的接口功能。LEVB内部装有一个16位的非易失性DDR3 SDRAM，该设计可以生成16位测试数据，并将数据写入板载RAM。接着，设计会读取DDR3 SDRAM中的数据，并与预设的期望数据进行比较。如果读取的数据与标准数据存在差异，设计会触发错误信号指示。此外，用户可以通过板载的DIP开关调整设计参数，以进行不同的运行模式。
文档内容详尽地介绍了演示电路的设计原理和搭建流程，包括如何配置硬件环境、设置正确的时序参数以及调试步骤。通过这个DDR3 Demo，用户不仅可以理解ECP3在高速存储器控制中的工作原理，还能学习到如何优化性能和处理常见问题，从而提升自己的设计技能。
对于想要在嵌入式系统或FPGA应用中使用DDR3内存的工程师而言，这是一份极其实用的参考材料，涵盖了从理论到实践的全方位指导。通过遵循这份用户指南，开发者可以确保他们的设计能够充分利用Lattice ECP3的高性能特性，并有效地集成到自己的项目中。
3
DDR3 Demo for the
Lattice Semiconductor LatticeECP3 Versa Evaluation Board
Figure 1. DDR3 Demo Design Block Diagram
CSM
14-Segment LED Driver
Command Generator
(State Machine)
Address Generator
Write Data Generator
Read Data Validator
LatticeECP3-35EA
DDR_ulogic
DDR3 Memory
Controller
Local User
Interface
100MHz DDR3
Clock Input
200MHz
SCLK
On-Board
DDR3
SDRAM
DDR3
Inteface
6-Bit DIP Switch
7 Output LEDs
DDR3 SDRAM Controller IP Core
The IP core used to generate the DDR3 controller core is the DDR3 SDRAM Controller IP core, version 1.2. The
user must install version 1.2 before generating the IP core and running the demo. The core generated with this IP
core interfaces directly with the external, on-board DDR3 SDRAM and performs control operations. The demo has
been designed to support a DDR3 data bus width of 16 bits since the DDR3 memory module installed in the
LatticeECP3 Versa Evaluation Board is 16 bits wide. See EB62, the
LatticeECP3 Versa Development Kit User’s
Guide for further information on the DDR3 SDRAM module used in this demo. Once a DDR3 core is generated with
a supported data width, the whole demo design can be simulated and implemented without modifying the code. A
DDR3
IP core configuration file (ddr3core.lpc) is provided in the demo package. This configuration file should be
used to make changes to the core and/or regenerate the core. In the Linux platform, the DDR3 SDRAM Controller
IP core should be downloaded, uncompressed and placed in the folder diamond/1.2/module. The DDR3 SDRAM
Controller IP core will appear in the IP core tree.
User Logic
The user logic implemented in the DDR3 demo design provides the following functions:
• State machine programs the mode registers and controls DDR3 read and write operations
• Address generation
• Write data generation
• Read data validation
• Control and observation
Demo Control State Machine
The state machine controls the demo using the user control input through a 6-bit DIP switch. Once the Lat-
t
iceECP3 device is programmed or a system reset is applied by pressing the GSR button, the state machine pro-
grams all DDR3 mode registers (MR0~MR3) based on the user test
configuration (DIP switch setting). Then, it gen-
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