Renesas Synergy S1 Series Microcontroller User's Manual

需积分: 5 148 浏览量更新于2024-07-09 收藏 14.45MB PDF 举报

"Renesas Synergy S128 Microcontroller User's Manual" Renesas Synergy S128是一款微控制器，属于Renesas Synergy平台的S1系列，专为数字可寻址照明接口（DALI）通信设计了一个集成模块，符合IEC62386版本2（DALI2）标准。该手册发布于2018年11月，版本1.10，包含了产品和产品规格的详细信息，但需要注意的是，这些信息可能会随着Renesas Electronics Corp.的更新而变化，用户应定期通过Renesas的官方网站获取最新的信息。 S128微控制器组是一个高性能的嵌入式处理解决方案，可能包括一系列功能特性，如高效的CPU内核、丰富的外设接口、大容量的存储器以及低功耗设计。这些特性使其适用于各种工业自动化、智能家居、智能照明以及其他需要精确控制和高效通信的嵌入式应用。用户手册将提供关于S128微控制器的详细使用指南，包括硬件配置、软件开发、系统集成以及故障排查等方面的内容。手册中的电路描述和软件示例仅用于展示半导体产品的操作和应用实例，但设计人员在将这些电路、软件或信息应用于产品或系统设计时需自行承担责任。Renesas Electronics对此不承担任何直接或间接的责任。手册中可能还会涉及以下关键知识点： 1. **DalI2协议**：DALI2是一种国际标准的双向通信协议，用于控制和管理照明设备，提供了更高级别的控制灵活性和互操作性。 2. **嵌入式软件开发**：用户手册将涵盖如何使用适合的软件和硬件与DALI集成模块配合，以实现DALI2兼容的通信。 3. **硬件接口**：手册会详细介绍S128微控制器的外部接口，包括GPIO、UART、SPI、I2C等，以及如何配置它们来满足特定应用需求。 4. **电源管理**：由于S128是针对低功耗应用设计的，手册将涵盖如何优化电源配置以延长电池寿命。 5. **调试工具和开发环境**：手册可能包含如何使用Renesas的开发工具链，如IDE、编译器、调试器等进行程序开发和测试的步骤。 6. **安全特性**：S128可能包含安全相关的功能，如加密引擎、安全启动和安全更新机制，以保护系统免受恶意攻击。 7. **应用示例**：手册可能会提供实际应用案例，帮助开发者理解如何在不同场景下有效利用S128微控制器。通过深入理解和应用Renesas Synergy S128微控制器用户手册中的信息，开发者能够充分利用这款微控制器的潜力，创建出高效、可靠且符合最新标准的嵌入式系统。

12.6 Return from Low Power Modes .......................................................................................... 198

12.6.1 Return from Sleep Mode ............................................................................................ 198

12.6.2 Return from Software Standby Mode ......................................................................... 198

12.6.3 Return from Snooze Mode ......................................................................................... 199

12.7 Using the WFI Instruction with Non-maskable Interrupt ..................................................... 199

12.8 Reference ........................................................................................................................... 199

13. Buses............................................................................................................................................ 200

13.1 Overview............................................................................................................................. 200

13.2 Description of Buses........................................................................................................... 201

13.2.1 Main Buses................................................................................................................. 201

13.2.2 Slave Interface............................................................................................................ 201

13.2.3 Parallel Operation.......................................................................................................201

13.2.4 Constraints ................................................................................................................. 201

13.3 Register Descriptions.......................................................................................................... 202

13.3.1 Master Bus Control Register (BUSMCNT<master>) .................................................. 202

13.3.2 Slave Bus Control Register (BUSSCNT<slave>) ....................................................... 202

13.3.3 Bus Error Address Register (BUSnERRADD) (n = 3, 4) ............................................ 203

13.3.4 BUS Error Status Register (BUSnERRSTAT) (n = 3, 4)............................................. 204

13.4 Bus Error Monitoring Section.............................................................................................. 204

13.4.1 Error Type that Occurs by Bus ................................................................................... 204

13.4.2 Operation when a Bus Error Occurs........................................................................... 205

13.4.3 Conditions Leading to Illegal Address Access Errors................................................. 205

13.4.4 Timeout....................................................................................................................... 205

13.5 References ......................................................................................................................... 205

14. Memory Protection Unit (MPU)..................................................................................................... 206

14.1 Overview............................................................................................................................. 206

14.2 CPU Stack Pointer Monitor................................................................................................. 207

14.2.1 Protection of Registers ............................................................................................... 209

14.2.2 Overflow/Underflow Error ........................................................................................... 209

14.2.3 Register Descriptions ................................................................................................. 210

14.2.3.1 Main Stack Pointer (MSP) Monitor Start Address Register (MSPMPUSA) ....... 210

14.2.3.2 Main Stack Pointer (MSP) Monitor End Address Register (MSPMPUEA

) ......... 210

14.2.3.3 Process Stack Pointer (PSP) Monitor Start Address Register (PSPMPUSA) .... 211

14.2.3.4 Process Stack Pointer (PSP) Monitor End Address Register (PSPMPUEA) ..... 211

14.2.3.5 Stack Pointer Monitor Operation After Detection Register (MSPMPUOAD, PSPM-

PUOAD) ............................................................................................................. 212

14.2.3.6 Stack Pointer Monitor Access Control Register (MSPMPUCTL, PSPMPUCTL)212

14.2.3.7 Stack Pointer Monitor Protection Register (MSPMPUPT, PSPMPUPT) ............ 213

14.3 Arm MPU ............................................................................................................................ 214

14.4 Bus Master MPU................................................................................................................. 214

14.4.1 Register Descriptions ................................................................................................. 215

14.4.1.1 Group A Region n Start Address Register (MMPUSAn) (n = 0 to 3).................. 216

14.4.1.2 Group A Region n End Address Register (MMPUEAn) (n = 0 to 3)................... 216

14.4.1.3 Group A Region n Access Control Register (MMPUACAn) (n = 0 to 3)............. 216

14.4.1.4 Bus Master MPU Control Register (MMPUCTLA).............................................. 218

14.4.1.5 Group A Protection of Register (MMPUPTA) ..................................................... 218

14.4.2 Functions .................................................................................................................... 219

14.4.2.1 Protection of registers ........................................................................................ 221

14.4.2.2 Memory protection error ..................................................................................... 221

14.5 Bus Slave MPU................................................................................................................... 221

14.5.1 Register Descriptions ................................................................................................. 222

14.5.1.1 Access Control Register for Memory Bus 1 (SMPUMBIU)................................. 222

14.5.1.2 Access Control Register for Internal Peripheral Bus 9 (SMPUFBIU) ................. 223

14.5.1.3 Access Control Register for Memory Bus 4 (SMPUSRAM0) ............................. 223

14.5.1.4 Access Control Register for Internal Peripheral Bus 1 (SMPUP0BIU)............... 224

14.5.1.5 Access Control Register for Internal Peripheral Bus 3 (SMPUP2BIU)............... 225

14.5.1.6 Access Control Register for Internal Peripheral Bus 7 (SMPUP6BIU)............... 225

14.5.1.7 Slave MPU Control Register (SMPUCTL).......................................................... 226

14.5.2 Functions .................................................................................................................... 227

14.5.2.1 Memory protection.............................................................................................. 227

14.5.2.2 Protection of registers ........................................................................................ 227

14.5.2.3 Memory protection error ..................................................................................... 227

14.6 Security MPU...................................................................................................................... 227

14.6.1 Register Descriptions (Option-Setting memory)......................................................... 228

14.6.1.1 Security MPU Program Counter Start Address Register n (SECMPUPCSn)

(n = 0, 1)............................................................................................................. 228

14.6.1.2 Security MPU Program Counter End Address Register n (SECMPUPCEn)

(n = 0, 1)............................................................................................................. 229

14.6.1.3 Security MPU Region 0 Start Address Register (SECMPUS0).......................... 229

14.6.1.4 Security MPU Region 0 End Address Register (SECMPUE0)........................... 230

14.6.1.5

Security MPU Region 1 Start Address Register (SECMPUS1).......................... 230

14.6.1.6 Security MPU Region 1 End Address Register (SECMPUE1)........................... 231

14.6.1.7 Security MPU Region 2 Start Address Register (SECMPUS2).......................... 231

14.6.1.8 Security MPU Region 2 End Address Register (SECMPUE2)........................... 232

14.6.1.9 Security MPU Region 3 Start Address Register (SECMPUS3).......................... 232

14.6.1.10 Security MPU Region 3 End Address Register (SECMPUE3)........................... 233

14.6.1.11 Security MPU Access Control Register (SECMPUAC) ...................................... 233

14.6.2 Memory Protection ..................................................................................................... 234

14.6.3 Usage Notes............................................................................................................... 235

14.7 References ......................................................................................................................... 235

15. Data Transfer Controller (DTC)..................................................................................................... 236

15.1 Overview............................................................................................................................. 236

15.2 Register Descriptions.......................................................................................................... 237

15.2.1 DTC Mode Register A (MRA)..................................................................................... 238

15.2.2 DTC Mode Register B (MRB)..................................................................................... 238

15.2.3 DTC Transfer Source Register (SAR) ........................................................................ 239

15.2.4 DTC Transfer Destination Register (DAR) ................................................................. 240

15.2.5 DTC Transfer Count Register A (CRA) ...................................................................... 240

15.2.6 DTC Transfer Count Register B (CRB) ..................................................................... 241

15.2.7 DTC Control Register (DTCCR) ................................................................................. 241

15.2.8 DTC Vector Base Register (DTCVBR) ....................................................................... 242

15.2.9 DTC Module Start Register (DTCST) ......................................................................... 242

15.2.10 DTC Status Register (DTCSTS) ................................................................................. 242

15.3 Activation Sources.............................................................................................................. 243

15.3.1 Allocating Transfer Information and DTC Vector Table.............................................. 243

15.4 Operation............................................................................................................................ 245

15.4.1 Transfer Information Read Skip Function................................................................... 248

15.4.2 Transfer Information Write-Back Skip Function.......................................................... 248

15.4.3 Normal Transfer Mode................................................................................................ 249

15.4.4 Repeat Transfer Mode................................................................................................ 250

15.4.5 Block Transfer Mode ................................................................................................. 251

15.4.6 Chain Transfer............................................................................................................ 252

15.4.7 Operation Timing........................................................................................................ 253

15.4.8 Execution Cycles of DTC............................................................................................ 254

15.4.9 DTC Bus Mastership Release Timing ........................................................................ 255

15.5 DTC Setting Procedure....................................................................................................... 255

15.6 Examples of DTC Usage .................................................................................................... 256

15.6.1 Normal Transfer..........................................................................................................256

15.6.2 Chain transfer ............................................................................................................. 257

15.6.3 Chain Transfer when Counter = 0 .............................................................................. 259

15.7 Interrupt Source.................................................................................................................. 260

15.8 Event Link........................................................................................................................... 260

15.9 Snooze Control Interface.................................................................................................... 260

15.10 Module-Stop Function......................................................................................................... 260

15.11 Usage Notes....................................................................................................................... 261

15.11.1 Transfer Information Start Address ............................................................................ 261

16. Event Link Controller (ELC) ......................................................................................................... 262

16.1 Overview............................................................................................................................. 262

16.2 Register Descriptions.......................................................................................................... 263

16.2.1 Event Link Controller Register (ELCR)....................................................................... 263

16.2.2 Event Link Software Event Generation Register n (ELSEGRn) where n = 0, 1 ......... 263

16.2.3 Event Link Setting Register n (ELSRn) ...................................................................... 264

16.3 Operation............................................................................................................................ 267

16.3.1 Relation between Interrupt Handling and Event Linking............................................. 267

16.3.2 Linking Events ............................................................................................................ 268

16.3.3 Example Procedure for Linking Events ...................................................................... 268

16.4 Usage Notes....................................................................................................................... 268

16.4.1 Linking DTC Transfer End Signals as Events ............................................................ 268

16.4.2 Setting the Clocks.......................................................................................................268

16.4.3 Module-Stop Function Setting .................................................................................... 268

16.4.4 ELC Delay Time ......................................................................................................... 269

17. I/O Ports........................................................................................................................................ 270

17.1 Overview............................................................................................................................. 270

17.2 Register Descriptions.......................................................................................................... 272

17.2.1 Port Control Register 1 (PCNTR1/PODR/PDR) ........................................................ 272

17.2.2 Port Control Register 2 (PCNTR2/EIDR/PIDR) .......................................................... 273

17.2.3 Port Control Register 3 (PCNTR3/PORR/POSR)....................................................... 274

17.2.4 Port Control Register 4 (PCNTR4/EORR/EOSR)....................................................... 275

17.2.5 Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY)

(m = 0 to 5, 9; n = 00 to 15) ........................................................................................ 276

17.2.6 Write-Protect Register (PWPR) .................................................................................. 278

17.3 Operation............................................................................................................................ 278

17.3.1 General I/O Ports........................................................................................................278

17.3.2 Port Function Select ................................................................................................... 278

17.3.3 Port Group Function for the ELC................................................................................ 279

17.3.3.1 Behavior when ELC_PORT1 or 2 is input from the ELC.................................... 279

17.3.3.2 Behavior when an event pulse is output to the ELC........................................... 280

17.4 Handling of Unused Pins ....................................................................................................280

17.5 Usage Notes....................................................................................................................... 281

17.5.1 Procedure for Specifying Pin Function ....................................................................... 281

17.5.2 Procedure to Use Port Group Input........................

.................................................... 281

17.5.3 Port Output Data Register (PODR) Summary ............................................................ 281

17.5.4 Notes on Use of Analog Functions............................................................................. 282

17.5.5 Selecting the USB_DP and USB_DM Pins ................................................................ 282

17.5.5.1 Notes on Using P914/USB_DP and P915/USB_DM.......................................... 282

17.6 Peripheral Select Settings for each product ....................................................................... 282

18. Key Interrupt Function (KINT)....................................................................................................... 288

18.1 Overview............................................................................................................................. 288

18.2 Register Descriptions.......................................................................................................... 290

18.2.1 Key Return Control Register (KRCTL) ....................................................................... 290

18.2.2 Key Return Flag Register (KRF)................................................................................. 290

18.2.3 Key Return Mode Register (KRM).............................................................................. 290

18.3 Operation............................................................................................................................ 291

18.3.1 When Not Using Key Interrupt Flag (KRMD = 0)........................................................ 291

18.3.2 When Using Key Interrupt Flag (KRMD = 1) .............................................................. 291

18.4 Usage Note......................................................................................................................... 293

19. Port Output Enable for GPT (POEG)............................................................................................ 294

19.1 Overview............................................................................................................................. 294

19.2 Register Descriptions.......................................................................................................... 296

19.2.1 POEG Group n Setting Register (POEGGn) (n = A, B).............................................. 296

19.3 Output-Disable Control Operation ...................................................................................... 297

19.3.1 Pin Input Level Detection Operation........................................................................... 297

19.3.1.1 Digital filter.......................................................................................................... 297

19.3.2 Output-Disable Request from GPT............................................................................. 298

19.3.3 Comparator Interrupt Detection.................................................................................. 298

19.3.4 Output Disable Control on Detection of Stopped Oscillation...................................... 298

19.3.5 Output Disable Control Using Registers..................................................................... 298

19.3.6 Release from Output Disable ..................................................................................... 298

19.4 Interrupt Source.................................................................................................................. 299

19.5 External Trigger Output to GPT.......................................................................................... 299

19.6 Usage Notes....................................................................................................................... 300

19.6.1 Transition to Software Standby mode ........................................................................ 300

19.6.2 Specifying Pins Associated with the GPT................................................................... 300

20. General PWM Timer (GPT) .......................................................................................................... 301

20.1 Overview............................................................................................................................. 301

20.2 Register Descriptions.......................................................................................................... 305

20.2.1 General PWM Timer Write-Protection Register (GTWP) ........................................... 306

20.2.2 General PWM Timer Software Start Register (GTSTR) ............................................. 306

20.2.3 General PWM Timer Software Stop Register (GTSTP) ............................................. 307

20.2.4 General PWM Timer Software Clear Register (GTCLR)............................................ 307

20.2.5 General PWM Timer Start Source Select Register (GTSSR)..................................... 308

20.2.6 General PWM Timer Stop Source Select Register (GTPSR)..................................... 310

20.2.7 General PWM Timer Clear Source Select Register (GTCSR) ................................... 312

20.2.8 General PWM Timer Up Count Source Select Register (GTUPSR) .......................... 315

20.2.9 General PWM Timer Down Count Source Select Register (GTDNSR)...................... 317

20.2.10 General PWM Timer Input Capture Source Select Register A(GTICASR) ................ 320

20.2.11 General PWM Timer Input Capture Source Select Register B(GTICBSR) ................ 322

20.2.12 General PWM Timer Control Register (GTCR) .......................................................... 325

20.2.13 General PWM Timer Count Direction and Duty Setting Register (GTUDDTYC) ....... 326

20.2.14 General PWM Timer I/O Control Register (GTIOR) ................................................... 328

20.2.15 General PWM Timer Interrupt Output Setting Register (GTINTAD)........................... 332

20.2.16 General PWM Timer Status Register (GTST) ............................................................ 333

20.2.17 General PWM Timer Buffer Enable Register (GTBER).............................................. 336

20.2.18 General PWM Timer Counter (GTCNT) ..................................................................... 338

20.2.19 General PWM Timer Compare Capture Register n (GTCCRn) (n = A to F)............... 338

20.2.20 General PWM Timer Cycle Setting Register (GTPR)................................................. 339

20.2.21 General PWM Timer Cycle Setting Buffer Register (GTPBR).................................... 339

剩余1231页未读，继续阅读

SZZHANGSR

粉丝: 0
资源: 15

Renesas Synergy S1 Series Microcontroller User's Manual

ATmegaS128单片机.pdf

原创synergy-1.14.6.19-stable for ubuntu-20.04

synergy-subversion-iar-embedded-workbench.pdf

多功能酶标仪Gen5软件使用方法-Synergy-H4-.01155.pdf

synergy-1.7.3.zip

Synergy-MacOS.zip

synergy-core.rar

synergy-1.6.2.tar.gz

maven-scm-provider-synergy-1.2.jar

maven-scm-provider-synergy-1.3.jar

最新资源