FXLS8962AF: 超低功耗3轴MEMS加速度计数据手册

需积分: 5 88 浏览量更新于2024-07-04 收藏 2.42MB PDF 举报

FXLS8962AF是一款专为汽车（便利性和安全）、工业和医疗物联网应用设计的高性能低功耗三轴加速度传感器。该设备旨在满足各种独特使用场景对分辨率和功耗的不同需求，提供极高的灵活性。该产品具有以下几个关键特性： 1. 多功能测量范围：FXLS8962AF支持±2g、±4g、±8g和±16g的用户可选全量程，允许设计师根据具体应用选择最合适的测量精度。 2. 高分辨率与低功耗模式：传感器支持两种工作模式，即高性能模式和低功耗模式。在低功耗模式下，它能够显著减少系统的总能耗，非常适合那些对节能有严格要求的物联网设备。 3. 紧凑的封装：该器件采用2mm x 2mm x 0.95mm的10引脚DFN封装，引脚间距仅为0.4mm，适合于小型化设计，并且带有可湿性侧面，方便表面安装。 4. 严格的标准认证：FXLS8962AF通过了AEC-Q100认证，确保在-40°C至+105°C的宽温范围内稳定运行，满足严苛的工业环境和汽车电子应用的可靠要求。 5. 优化的系统集成：内置的高级数字功能简化了主机数据采集过程，减少了外围电路的复杂性，有助于整体设计的简化和成本降低。 FXLS8962AF凭借其卓越的性能、节能特性、小巧的封装以及广泛的温度适应性，成为物联网运动传感的理想选择，尤其适用于那些对功耗敏感且需要高精度的智能设备应用场景。无论是汽车仪表板、工业监控还是医疗健康监测设备，这款传感器都能提供强大而可靠的性能支撑。

NXP Semiconductors

FXLS8962AF

3-Axis Low-g Accelerometer

Product data sheet Rev. 5.3 — 10 December 2019

16 / 99

10 I

C digital interface

The registers embedded within FXLS8962AF may be accessed using an I

C interface

when the INTF_SEL pin is tied to GND. If the V

supply is not present, the device will

be in shutdown mode and any communications on the interface are ignored. When the

device is on a common I

C-bus with other slave devices, the V

supply pin must be left

unconnected (high-impedance) when the device supply is turned off to ensure that the

internal ESD protection diodes do not become forward biased and prevent the bus from

functioning normally (clamping).

The I

C slave interface port of FXLS8962AF is compliant with the following three

operating modes as defined in UM10204 I

C-bus specification and user manual, Rev. 6

April 2014:

• Fast-mode Plus (Fm+) at 1000 kHz

• Fast-mode (Fm) at 400 kHz

• Standard-mode (Sm) at 100 kHz

Table 9. I

C serial interface pin description

Pin Name Pin Description

SCL I

C serial clock (pull-up resistor is required)

SDA I

C serial data (pull-up resistor is required)

10.1 I

C interface characteristics

The I

C slave address (7-bit format) is set to 18h when SA0 = 0, and 19h when SA0 = 1.

Table 10. FXLS8962AF I

C read and write addresses

SA0 I

C write address I

C read address

0 30h (0011 0000b) 31h (0011 0001b)

1 32h (0011 0010b) 33h (0011 0011b)

Table 11. I

C slave timing values for Standard-mode (Sm) and Fast-mode (Fm), and Fast-mode Plus (Fm+)

C Standard-

mode

[1]

C Fast-mode

[1]

C Fast-mode Plus

[2]

Parameter Symbol

Min Max Min Max Min Max

Unit

SCL clock frequency f

SCL

0 100 0 400 0 1000 kHz

Bus free time between

STOP and START

conditions

BUF

4.7 — 1.3 — 0.5 — µs

Repeated START hold

time

HD;STA

4 — 0.6 — 0.26 — µs

Repeated START setup

time

SU;STA

4.7 — 0.6 — 0.26 — µs

STOP condition setup

time

SU;STO

4 — 0.6 — 0.26 — µs

SDA valid time

[3]

VD;DAT

— 3.45

[4]

— 0.9

[4]

— 0.45

[4]

µs

NXP Semiconductors

FXLS8962AF

3-Axis Low-g Accelerometer

Product data sheet Rev. 5.3 — 10 December 2019

17 / 99

C Standard-

mode

[1]

C Fast-mode

[1]

C Fast-mode Plus

[2]

Parameter Symbol

Min Max Min Max Min Max

Unit

SDA valid acknowledge

time

[5]

VD;ACK

— 3.45

[4]

— 0.9

[4]

— 0.45

[4]

µs

SDA setup time t

SU;DAT

250 — 100

[6]

— 50 — ns

SCL clock low time t

LOW

4.7 — 1.3 — 0.50 — µs

SCL clock high time t

HIGH

4.0 — 0.6 — 0.26 — µs

SDA and SCL rise time t

— 1000 20 300 — 120 ns

SDA and SCL fall

time

[7][8]

— 300 20*(V

/5.5) 300 20*(V

/5.5)

[2]

120 ns

Pulse width of spikes on

SDA and SCL that are

suppressed by the input

filter

0 50 0 50 0 50 ns

[1] All values referred to VIH(min) and VIL(max) levels.

[2] Needed to be backwards compatible with Fast mode.

[3] t

VD;DAT

referred to the time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

[4] The maximum t

HD;DAT

could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode respectively, but must be less than the maximum of t

VD;DAT

VD;ACK

by a transition time.

[5] t

VD;ACK

= time for ACK signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

[6] A Fast-mode I

C device can be used in a Standard mode I

C system, but the requirement t

SU;DAT

250 ns must then be met. Also the acknowledge timing

must meet this set-up time.

[7] The maximum t

for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t

is specified at 250 ns. This

allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum

specified t

[8] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when

considering bus timing.

SDA

SCL

SU:STA

HD:STA

SU:STO

VD:ACK

70%

30%

clock

BUF

Figure 10. I

C slave timing diagram for Standard-mode, Fast-mode and Fast-mode Plus

NXP Semiconductors

FXLS8962AF

3-Axis Low-g Accelerometer

Product data sheet Rev. 5.3 — 10 December 2019

18 / 99

10.1.1 General I

C operation

There are two signals associated with the I

C-bus: the Serial Clock Line (SCL) and the

Serial Data line (SDA). SDA is a bidirectional signal used for sending and receiving the

data to/from the interface. External pull-up resistors connected to V

are required for

SDA and SCL. When the I

C-bus is free, SCL and SDA are high.

The maximum practical operating frequency for I

C in a given system implementation

depends on several factors including the pull-up resistor and voltage values and total bus

capacitance (PCB trace + parasitic device capacitance(s)).

A transaction on the bus is started by the master through a start condition (ST) signal,

which is defined as a HIGH-to-LOW transition on SDA line while the SCL line is held

HIGH. After the ST signal has been transmitted by the master, the bus is considered

busy. The next byte of data transmitted contains the slave address in the first seven

bits, and the eighth bit, the read/write bit, indicates whether the master is receiving data

from the slave or transmitting data to the slave. When an address is sent, each device in

the system compares the first seven bits after the ST condition with its own address. If

they match, the device considers itself addressed by the master. The ninth clock pulse,

following the slave address byte (and each subsequent byte) is the acknowledge (ACK).

The transmitter must release the SDA line during the ACK period. The receiver must

then pull the data line low so that it remains stable low during the high period of the

acknowledge clock period.

The number of bytes per transfer is unlimited. If a receiver can't receive another complete

byte of data until it has performed some other function, it can hold the SCL line low to

force the transmitter into a wait state. Data transfer only continues when the receiver

is ready for another byte and releases the clock line. This delay action is called clock

stretching. Not all master devices support clock stretching. This device implements clock

stretching—the SCL line may be stretched (pulled low) for up to 1 µs when needed

during a read operation. Clock stretching, when applied, will occur after the ACK is

issued by the I

C bus master.

A LOW-to-HIGH transition on the SDA line while the SCL line is high is defined as a stop

condition (SP) signal. A write or burst write is always terminated by the master issuing

the SP signal. A master should properly terminate a read by not acknowledging a byte at

the appropriate time in the protocol, followed by the SP signal. A master may also issue a

repeated start signal (SR) during a transfer.

10.1.2 I

C read/write operations

10.1.2.1 Single byte read

The master transmits a start condition (ST) to FXLS8962AF, followed by the slave

address, with the R/W bit set to '0' for a write, and the FXLS8962AF sends an

acknowledgement. Then the master transmits the address of the register to read and

the FXLS8962AF sends an acknowledgement. The master transmits a repeated start

condition (SR), followed by the slave address with the R/W bit set to '1' for a read from

the previously selected register. The FXLS8962AF then acknowledges and transmits

the data from the requested register. The master does not acknowledge (NAK) the

transmitted data and then transmits a stop condition to end the data transfer.

10.1.2.2 Multiple byte read

When performing a multi-byte or burst read, FXLS8962AF automatically increments the

剩余98页未读，继续阅读

gushu114122

粉丝: 0
资源: 73

FXLS8962AF: 超低功耗3轴MEMS加速度计数据手册

FXLS8962AF Data sheet.pdf

w3af用户手册（中文版）

深信服下一代防火墙AF用户手册-V8.0.75-648页

M27128AF1的数据手册

imx585 datasheet数据手册完整版

西门子订货号315-2AF03-0AB0使用手册

如何使用w3af框架识别并利用Web应用中的SQL注入漏洞？请详细说明操作步骤与最佳实践。

如何根据《太航电子秤ACS-FB技术手册》配置电子秤的条码打印参数，并确保数据通讯的准确性？

function DeleteRpeat() global AP AM AF AN; [m,~]=size(AF); for i=1:m if i>m break; end F=AF(i,:); j=i+1; while j<m if eql(AF{j,1},F{1,1})&&eql(AF{j,2},F{1,2}) AP(j,:)=[]; AM(j,:)=[]; AF(j,:)=[]; AN(j,:)=[]; j=j-1; m=m-1; end j=j+1; end end end

=AF5 + AG5*365 修改公式 AG5单元格和AF5单元格没有数据则返回空值

最新资源