PIC10F320/322高性能微控制器数据手册：低功耗特性与功能概览

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本文档是Microchip Technology Inc.于2011年至2015年期间发布的关于PIC10(L)F320/322微控制器的数据手册。这款高性能RISC（Reduced Instruction Set Computing）CPU设计紧凑，仅需学习35条单周期指令，除了分支指令外，所有操作在一个时钟周期内完成。它支持高达16MHz的直流输入时钟，实现250ns的指令周期，表现出极高的执行效率。该微控制器的核心特性包括： 1. 八级深的硬件堆栈，确保了程序执行的上下文管理能力。 2. 内建中断处理功能，可以灵活响应外部事件，提高系统响应速度。 3. 通过处理器自我写入/读取程序内存，允许在运行时修改代码，增强了程序的灵活性。 4. 与其它6引脚的PIC10FXXX系列微控制器的引脚兼容，方便集成到现有电路板上。 5. 存储器配置强大，提供512字节的闪存程序存储空间，以及64字节的数据存储区域，其中数据闪存具有高耐久性（HEF），支持128字节的非易失性数据存储，可进行10万次擦写/写入操作。 6. 特殊功能方面，该微控制器配备低功耗16MHz内部振荡器，支持软件频率选择范围从16MHz到31kHz，出厂时经过1%典型精度校准。此外，它还支持宽广的工作电压范围，从1.8V到3.6V（PIC10LF320/322）或2.3V到5.5V。 7. 内置电源管理功能包括电源-on复位（POR）、电源上升定时器（PWRT）、棕色-out复位（BOR）等，能有效保护设备在不同供电条件下正常工作。 8. 配备超低功耗睡眠稳压器和扩展看门狗定时器（WDT），用于长时间运行和系统稳定性维护。 9. 支持可编程代码保护，确保代码的安全性。 10. 提供多种省电模式，如睡眠模式，降低功耗的同时保持有限的唤醒能力。 11. 可选的振荡器选项包括外部时钟（EC模式）和内部振荡器，适应不同的应用需求。 12. 最后，微控制器还支持在电路板上的无损串行通信接口（In-Circuit Serial Programming），便于调试和升级。总结来说，PIC10(L)F320/322是一款功能强大的、低功耗且易于使用的微控制器，适合各种嵌入式系统应用，无论是快速响应的实时控制，还是对存储容量和电池寿命有较高要求的设备。

PIC10(L)F320/322

DS40001585D-page 16  2011-2015 Microchip Technology Inc.

Bank 0 (Continued)

20h PMADRL PMADR<7:0> 0000 0000 0000 0000

21h PMADRH

— — — — — — — PMADR8 ---- ---0 ---- ---0

22h PMDATL PMDAT<7:0> xxxx xxxx uuuu uuuu

23h PMDATH

— —PMDAT<13:8>--xx xxxx --uu uuuu

24h PMCON1

— CFGS LWLO FREE WRERR WREN WR RD 1000 0000 1000 q000

25h PMCON2 Program Memory Control Register 2 (not a physical register) 0000 0000 0000 0000

26h CLKRCON

—CLKROE— — — — — — -0-- ---- -0-- ----

27h NCO1ACCL NCO1 Accumulator <7:0> 0000 0000 0000 0000

28h NCO1ACCH NCO1 Accumulator <15:8> 0000 0000 0000 0000

29h NCO1ACCU

— NCO1 Accumulator <19..16> ---- 0000 ---- 0000

2Ah NCO1INCL NCO1 Increment <7:0> 0000 0001 0000 0001

2Bh NCO1INCH NCO1 Increment <15:8> 0000 0000 0000 0000

2Ch

— Unimplemented — —

2Dh NCO1CON N1EN N1OE N1OUT N1POL

— — —N1PFM0000 ---0 00x0 ---0

2Eh NCO1CLK

N1PWS<2:0> — — —N1CKS<1:0>

000- --00 000- --00

2Fh

Reserved Reserved xxxx xxxx uuuu uuuu

30h WDTCON

— —WDTPS<4:0>SWDTEN--01 0110 --01 0110

31h

CLC1CON

LC1EN LC1OE LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 00x0 -000 00x0 -000

32h

CLC1SEL0

— LC1D2S<2:0> — LC1D1S<2:0> -xxx -xxx -uuu -uuu

33h

CLC1SEL1

— LC1D4S<2:0> — LC1D3S<2:0> -xxx -xxx -uuu -uuu

34h

CLC1POL

LC1POL

— — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu

35h

CLC1GLS0

LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N

xxxx xxxx uuuu uuuu

36h

CLC1GLS1

LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N

xxxx xxxx uuuu uuuu

37h

CLC1GLS2

LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N

xxxx xxxx uuuu uuuu

38h

CLC1GLS3

LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N

xxxx xxxx uuuu uuuu

39h CWG1CON0

G1EN G1OEB G1OEA G1POLB G1POLA

— —

G1CS0

0000 0--0 0000 0--0

3Ah CWG1CON1

G1ASDLB<1:0> G1ASDLA<1:0>

— —

G1IS<1:0>

xxxx --xx uuuu --uu

3Bh CWG1CON2 G1ASE G1ARSEN

— — — — G1ASDCLC1 G1ASDFLT xx-- --xx uu-- --uu

3Ch CWG1DBR

— —CWG1DBR<5:0>--xx xxxx --uu uuuu

3Dh CWG1DBF

— —CWG1DBF<5:0>--xx xxxx --uu uuuu

3Eh

VREGCON

— — — — — —VREGPM1Reserved ---- --01 ---- --01

3Fh

BORCON

SBOREN BORFS — — — — — BORRDY 10-- ---q uu-- ---u

TABLE 2-3: SPECIAL FUNCTION REGISTER SUMMARY (BANK 0) (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all

other resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: Unimplemented, read as ‘1’.

 2011-2015 Microchip Technology Inc. DS40001585D-page 17

PIC10(L)F320/322

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 2-3 shows the two

situations for the loading of the PC. The upper example

in Figure 2-3 shows how the PC is loaded on a write to

PCL (PCLATH<4:0>  PCH). The lower example in

Figure 2-3 shows how the PC is loaded during a CALL or

GOTO instruction (PCLATH<4:3>  PCH).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<12:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by

writing the desired upper five bits to the PCLATH

PCL register, all 13 bits of the program counter will

change to the values contained in the PCLATH register

and those being written to the PCL register.

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). Care should be

exercised when jumping into a look-up table or

program branch table (computed GOTO) by modifying

the PCL register. Assuming that PCLATH is set to the

table start address, if the table length is greater than

255 instructions or if the lower eight bits of the memory

address rolls over from 0xFF to 0x00 in the middle of

the table, then PCLATH must be incremented for each

address rollover that occurs between the table

beginning and the target location within the table.

For more information refer to Application Note AN556,

“Implementing a Table Read” (DS00556).

2.3.2 STACK

All devices have an 8-level x 13-bit wide hardware

stack (see Figure 2-1). The stack space is not part of

either program or data space and the Stack Pointer is

not readable or writable. The PC is PUSHed onto the

stack when a CALL instruction is executed or an inter-

rupt causes a branch. The stack is POPed in the event

of a RETURN, RETLW or a RETFIE instruction

execution. PCLATH is not affected by a PUSH or POP

operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

2.4 Indirect Addressing, INDF and

FSR Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

actually accesses data pointed to by the File Select

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR and the IRP bit of the

STATUS register, as shown in Figure 2-4.

A simple program to clear RAM location 40h-7Fh using

indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

12 8 7 0

PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO, CALL

OPCODE <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

Note 1: There are no Status bits to indicate Stack

Overflow or Stack Underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interrupt address.

MOVLW 0x40 ;initialize pointer

MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer

BTFSS FSR,7 ;all done?

GOTO NEXT ;no clear next

CONTINUE ;yes continue

PIC10(L)F320/322

DS40001585D-page 20  2011-2015 Microchip Technology Inc.

3.2 Register Definitions: Configuration Word

U-1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1

R/P-1/1

— WRT<1:0> BORV LPBOR

LVP

bit 13 bit 8

R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1

R/P-1/1

CP MCLRE PWRTE WDTE<1:0> BOREN<1:0>

FOSC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared P = Programmable bit

bit 13 Unimplemented: Read as ‘1’

bit 12-11 WRT<1:0>: Flash Memory Self-Write Protection bits

256 W Flash memory: PIC10(L)F320:

11 =Write protection off

10 =000h to 03Fh write-protected, 040h to 0FFh may be modified by PMCON control

01 =000h to 07Fh write-protected, 080h to 0FFh may be modified by PMCON control

00 =000h to 0FFh write-protected, no addresses may be modified by PMCON control

512 W Flash memory: PIC10(L)F322:

11 =Write protection off

10 =000h to 07Fh write-protected, 080h to 1FFh may be modified by PMCON control

01 =000h to 0FFh write-protected, 100h to 1FFh may be modified by PMCON control

00 =000h to 1FFh write-protected, no addresses may be modified by PMCON control

bit 10 BORV: Brown-out Reset Voltage Selection bit

1 = Brown-out Reset voltage (VBOR), low trip point selected.

0 = Brown-out Reset voltage (V

BOR), high trip point selected.

bit 9 LPBOR: Low-Power Brown-out Reset Enable bit

1 = Low-power Brown-out Reset is enabled

0 = Low-power Brown-out Reset is disabled

bit 8 LVP: Low-Voltage Programming Enable bit

1 = Low-Voltage Programming enabled. MCLR/VPP pin function is MCLR.

0 = High Voltage on MCLR

/VPP must be used for programming

bit 7 CP: Code Protection bit

(2)

1 = Program memory code protection is disabled

0 = Program memory code protection is enabled

bit 6 MCLRE: MCLR

/VPP Pin Function Select bit

If LVP bit =

This bit is ignored.

If LVP bit =

1 =MCLR

/VPP pin function is MCLR; Weak pull-up enabled.

0 =MCLR

/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUA3 bit.

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: Once enabled, code-protect can only be disabled by bulk erasing the device.

3: See V

BOR parameter for specific trip point voltages.

剩余192页未读，继续阅读

plmm1314

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