"RH850U2A MCU开发必备：英文Datasheet与用户手册"

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The RH850U2A datasheet in English is an essential resource for MCU development, providing detailed information on the Renesas microcontroller RH850 Family. This comprehensive document, available on the Renesas website, offers in-depth descriptions of the product and its specifications as of October 2021. Users can refer to the user's manual for hardware guidance, including the RH850/U2A-EVA Group. It is important to note that all information contained in the datasheet is subject to change by Renesas Electronics Corp. without notice, so it is recommended to access the latest updates through various channels, such as the company's website. This datasheet is a crucial tool for developers and engineers looking to leverage the capabilities of the RH850U2A MCU for their projects. By providing clear and detailed information, it helps ensure successful implementation and optimal performance of the microcontroller in various applications.

9.3 Interrupt Requests and Error Notifications.................................................................................. 763

9.4 Registers..................................................................................................................................... 764

9.4.1 List of Registers................................................................................................................ 764

9.4.2 Reset of Registers............................................................................................................ 767

9.4.3 STAC_DPRAM — RAM Initialization Mode Control Register for DPRAM ....................... 769

9.4.4 STAC_DTSRAM — RAM Initialization Mode Control Register for DTSRAM ................... 770

9.4.5 STAC_GTM — RAM Initialization Mode Control Register for GTM ................................ 771

9.4.6 STAC_MSPI — RAM Initialization Mode Control Register for MSPI................................ 772

9.4.7 STAC_MMCA — RAM Initialization Mode Control Register for MMCA ........................... 774

9.4.8 SWMRESA_RSCFD— Software Module Reset Assertion Register for RS-CANFD ....... 775

9.4.9 SWMRESS_RSCFD — Software Module Reset Status Register for RS-CANFD ........... 776

9.4.10 SWMRESA_FLXA — Software Module Reset Assertion Register for FLXA ................... 777

9.4.11 SWMRESS_FLXA — Software Module Reset Status Register for FLXA ........................ 778

9.4.12 SWMRESA_GTM — Software Module Reset Assertion Register for GTM ..................... 779

9.4.13 SWMRESS_GTM — Software Module Reset Status Register for GTM .......................... 780

9.4.14 SWMRESA_ETNB— Software Module Reset Assertion Register for ETNB ................... 781

9.4.15 SWMRESS_ETNB — Software Module Reset Status Register for ETNB....................... 782

9.4.16 SWMRESA_RSENT — Software Module Reset Assertion Register for RSENT............. 783

9.4.17 SWMRESS_RSENT — Software Module Reset Status Register for RSENT.................. 784

9.4.18 SWMRESA_MSPI — Software Module Reset Assertion Register for MSPI ................... 785

9.4.19 SWMRESS_MSPI — Software Module Reset Status Register for MSPI......................... 786

9.4.20 SWMRESA_RLIN3 — Software Module Reset Assertion Register for RLIN3 ................. 787

9.4.21 SWMRESS_RLIN3 — Software Module Reset Status Register for RLIN3...................... 789

9.4.22 SWMRESA_ADCJ_ISO — Software Module Reset Assertion Register for ADCJ (ISO). 791

9.4.23 SWMRESS_ADCJ_ISO — Software Module Reset Status Register for ADCJ (ISO)...... 792

9.4.24 SWMRESA_CXPI — Software Module Reset Assertion Register for CXPI..................... 793

9.4.25 SWMRESS_CXPI — Software Module Reset Status Register for CXPI ......................... 794

9.4.26 SWMRESA_MMCA — Software Module Reset Assertion Register for MMCA ............... 795

9.4.27 SWMRESS_MMCA — Software Module Reset Status Register for MMCA .................... 796

9.4.28 SWMRESA_ENCA — Software Module Reset Assertion Register for ENCA ................. 797

9.4.29 SWMRESS_ENCA — Software Module Reset Status Register for ENCA ...................... 798

9.4.30 SWMRESA_PSI5 — Software Module Reset Assertion Register for PSI5...................... 799

9.4.31 SWMRESS_PSI5 — Software Module Reset

Status Register for PS

I5........................... 800

9.4.32 SWMRESA_PSI5S — Software Module Reset Assertion Register for PSI5-S................ 801

9.4.33 SWMRESS_PSI5S — Software Module Reset Status Register for PSI5-S .................... 802

9.4.34 SWMRESA_PWMD — Software Module Reset Assertion Register for PWM-Diag......... 803

9.4.35 SWMRESS_PWMD — Software Module Reset Status Register for PWM-Diag ............. 804

9.4.36 SWMRESA_RHSIF — Software Module Reset Assertion Register for RHSIF ............... 805

9.4.37 SWMRESS_RHSIF — Software Module Reset Status Register for RHSIF..................... 806

9.4.38 SWMRESA_RIIC — Software Module Reset Assertion Register for RIIC....................... 807

9.4.39 SWMRESS_RIIC — Software Module Reset Status Register for RIIC............................ 808

9.4.40 SWMRESA_SCI3 — Software Module Reset Assertion Register for SCI3 ..................... 809

9.4.41 SWMRESS_SCI3 — Software Module Reset Status Register for SCI3 .......................... 810

9.4.42 SWMRESA_SFMA — Software Module Reset Assertion Register for SFMA ................. 811

9.4.43 SWMRESS_SFMA — Software Module Reset Status Register for SFMA ...................... 812

9.4.44 SWMRESA_TAPA — Software Module Reset Assertion Register for TAPA .................. 813

9.4.45 SWMRESS_TAPA — Software Module Reset Status Register for TAPA ....................... 814

9.4.46 SWMRESA_TAUD — Software Module Reset Assertion Register for TAUD ................. 815

9.4.47 SWMRESS_TAUD — Software Module Reset Status Register for TAUD....................... 816

9.4.48 SWMRESA_TAUJ_ISO — Software Module Reset Assertion Register for TAUJ ........... 817

9.4.49 SWMRESS_TAUJ_ISO — Software Module Reset Status Register for TAUJ................ 818

9.4.50 SWMRESA_TPBA — Software Module Reset Assertion Register for TPBA................... 819

9.4.51 SWMRESS_TPBA — Software Module Reset Status Register for TPBA ....................... 820

9.4.52 SWMRESA_TSG3 — Software Module Reset Assertion Register for TSG3................... 821

9.4.53 SWMRESS_TSG3 — Software Module Reset Status Register for TSG3 ....................... 822

9.4.54 SWMRESA_OSTM — Software Module Reset Assertion Register for OSTM ................ 823

9.4.55 SWMRESS_OSTM — Software Module Reset Status Register for OSTM ..................... 824

9.4.56 RESFC — Reset Factor Clear Register ........................................................................... 825

9.4.57 RESFDDC — Reset Factor Clear Register for Debugger Disconnection Reset

[For U2A16, U2A8 and U2A6 Only].................................................................................. 827

9.4.58 RESKCPROT0 — Reset Controller Register Key Code Protection Register 0................ 828

9.4.59 BOOTCTRL — Boot Control Register.............................................................................. 829

9.4.60 SWSRESA — Software System Reset Assertion Register .............................................. 830

9.4.61 SWARESA — Software Application Reset Assertion Register ........................................ 831

9.4.62 RESC — Reset Configuration Register............................................................................ 832

9.4.63 RESF — Reset Factor Register ....................................................................................... 833

9.4.64 RESFDD — Reset Factor Register for Debugger Disconnection Reset

[For U2A16, U2A8 and U2A6 Only].................................................................................. 836

9.5 Operation.................................................................................................................................... 837

9.5.1 Reset Categories.............................................................................................................. 837

9.5.2 Reset Sources.................................................................................................................. 841

9.5.3 Reset Flags ...................................................................................................................... 844

9.5.4 Read Configuration Data from FLASH ............................................................................. 845

9.5.5 HW BIST........................................................................................................................... 845

9.5.6 RAM Initialization.............................................................................................................. 846

9.5.7 Start Up of Cores.............................................................................................................. 847

9.5.8 Reset Mask function......................................................................................................... 848

9.5.9 Reset Output (RESETOUT

) ............................................................................................ 848

Section 10 Power Supply Circuit.................................................................................... 849

10.1 Function...................................................................................................................................... 849

10.2 Power Supply Pins...................................................................................................................... 850

10.2.1 External Pin List................................................................................................................ 850

10.3 Block Diagram of Power Domains.............................................................................................. 852

10.4 Power Domains Arrangement..................................................................................................... 862

10.5 VDD Power Supply..................................................................................................................... 863

10.5.1 Features ........................................................................................................................... 863

10.5.2 Without SVR..................................................................................................................... 863

10.5.3 Using SVR........................................................................................................................ 864

10.6 SVR Controller ........................................................................................................................... 865

10.6.1 Features ........................................................................................................................... 865

10.6.2 Interrupt Requests and Error Notifications ....................................................................... 865

10.6.3 Input/Output Pins.............................................................................................................. 865

10.6.4 Setting Parameter............................................................................................................. 866

10.6.5 Basic Function.................................................................................................................. 867

10.7 Connection Example .................................................................................................................. 868

10.7.1 Example of Power Supply Connection for RH850/U2A-EVA ........................................... 868

10.8 Power Up/Down Timing.............................................................................................................. 869

10.9 Power Control in Debug Mode.................................................................................................... 870

10.10 SVR restriction............................................................................................................................ 871

Section 11 Power Supply Voltage Monitor..................................................................... 872

11.1 Overall Configuration.................................................................................................................. 872

11.2 Power On Clear .......................................................................................................................... 874

11.2.1 Features ........................................................................................................................... 874

11.2.2 Operation.......................................................................................................................... 874

11.3 Primary Detection of Voltage Monitor (VMON)........................................................................... 875

11.3.1 Features ........................................................................................................................... 875

11.3.2 Clock Supply..................................................................................................................... 877

11.3.3 Interrupt Requests and Error Notifications ....................................................................... 877

11.3.4 External Input/Outputs...................................................................................................... 877

11.3.5 Overview........................................................................................................................... 878

11.3.6 Registers .......................................................................................................................... 880

11.3.7 Operation.......................................................................................................................... 905

11.3.8 Usage Notes..................................................................................................................... 918

11.4 Delay Monitor (DMON) ............................................................................................................... 919

11.4.1 Features ........................................................................................................................... 919

11.4.2 Clock Supply..................................................................................................................... 919

11.4.3 Interrupt Requests and Error Notifications ....................................................................... 919

11.4.4 External Input/Outputs...................................................................................................... 919

11.4.5 Overview........................................................................................................................... 920

11.4.6 Registers .......................................................................................................................... 921

11.4.7 Operation.......................................................................................................................... 934

11.5 RAM Retention Voltage Indicator (Very Low Voltage Indicator, VLVI) ....................................... 943

11.5.1 Features ........................................................................................................................... 943

11.5.2 Clock Supply..................................................................................................................... 943

11.5.3 Interrupt Requests and Error Notifications ....................................................................... 943

11.5.4 External Input/Outputs...................................................................................................... 943

11.5.5 Registers .......................................................................................................................... 944

11.5.6 Operation.......................................................................................................................... 948

11.6 Usage Notes............................................................................................................................... 949

11.6.1 Judgment Method of the Reset Factors for Voltage Monitor............................................ 949

Section 12 Temperature Sensor (OTS) ......................................................................... 950

12.1 Features of Temperature Sensor for RH850/U2A-EVA.............................................................. 950

12.1.1 Number of Channels......................................................................................................... 950

12.1.2 Register Base Addresses ................................................................................................. 950

12.1.3 Clock Supply..................................................................................................................... 950

12.1.4 Interrupt Requests and Error Notifications ....................................................................... 950

12.1.5 Reset Sources .................................................................................................................. 951

12.1.6 External Input/Output Pins................................................................................................ 951

12.2 Overview..................................................................................................................................... 952

12.2.1 Functional Overview ......................................................................................................... 952

12.2.2 Block Diagram .................................................................................................................. 953

12.3 Register ...................................................................................................................................... 954

12.3.1 List of Registers................................................................................................................ 954

12.3.2 OTS0OTSTCR — Temperature Measurement Start Control Register............................. 955

12.3.3 OTS0OTENDCR — Temperature Measurement End Control Register........................... 956

12.3.4 OTS0OTCR — Temperature Sensor Control Register .................................................... 957

12.3.5 OTS0OTFCR — Temperature Sensor Flag Clear Register ............................................. 958

12.3.6 OTS0OTFR — Temperature Sensor Flag Register ......................................................... 959

12.3.7 OTS0OTSTR — Temperature Status Register ................................................................ 960

12.3.8 OTS0OTDR — Temperature Data Register..................................................................... 962

12.3.9 OTS0HTBRmn — High-Temperature Border mn Register

(m = A or B, n = U or L) .................................................................................................... 963

12.3.10 OTS0LTBRAn — Low-Temperature Border An Register (n = U or L).............................. 965

12.3.11 OTS0TDLR — Temperature Difference Limiting Register ............................................... 966

12.3.12 OTS0COEFFRn — Coefficient n Register (n = A, B, C) .................................................. 967

12.3.13 OTS0SDIAGCTL — Self-Diagnosis Control Register ...................................................... 968

12.4 Operation.................................................................................................................................... 969

12.4.1 Temperature Measurement Sequence............................................................................. 969

12.4.2 Examples of Temperature Measurement Operation ........................................................ 970

12.4.3 Temperature Measurement End Interrupt Request.......................................................... 972

12.4.4 Temperature Alarm Error and Temperature Rise /Drop Interrupt and Temperature

Sensor Error Interrupt Requests....................................................................................... 973

12.4.5 Self-Diagnosis Sequence ................................................................................................. 975

Section 13 Clock Controller ........................................................................................... 976

13.1 Features of Clock Controller ....................................................................................................... 976

13.1.1 External Input/Output Pins................................................................................................ 976

13.2 Type of Clocks ............................................................................................................................ 977

13.3 Configuration of Clock Controller................................................................................................ 979

13.3.1 Clock Generation Circuits................................................................................................. 980

13.3.2 Clock Setting Circuits ....................................................................................................... 981

13.4 Clock Oscillators ......................................................................................................................... 983

13.4.1 Main Oscillator (Main OSC).............................................................................................. 983

13.4.2 High Speed Internal Oscillator (HS IntOSC)..................................................................... 987

13.4.3 Low Speed Internal Oscillator (LS IntOSC) ...................................................................... 989

13.4.4 High Voltage Internal Oscillator (HV IntOSC)................................................................... 990

13.4.5 Phase Locked Loop (PLL) ................................................................................................ 991

13.5 Registers..................................................................................................................................... 993

13.5.1 Register Protection........................................................................................................... 993

13.5.2 List of Registers................................................................................................................ 993

13.5.3 Reset of Registers............................................................................................................ 995

13.5.4 Clock Oscillator Registers ................................................................................................ 997

13.5.5 Clock Selector/Divider Control Registers ....................................................................... 1005

13.5.6 Protection Register......................................................................................................... 1037

13.6 Operation.................................................................................................................................. 1038

13.6.1 Clock Setting .................................................................................................................. 1038

13.6.2 Stopping the Clock in Chip Standby Mode..................................................................... 1040

13.6.3 Stopping the Clock in Module Standby Mode................................................................. 1040

13.6.4 Clock Settings................................................................................................................. 1041

13.6.5 Sequence for Shifting the CPU System Clock Gear Up/Down....................................... 1043

13.6.6 CPU System Clock Setting in STOP/DeepSTOP Mode................................................. 1044

Section 14 Clock Monitor (CLMA)................................................................................ 1045

14.1 Features of RH850/U2A-EVA CLMA ........................................................................................ 1045

14.1.1 Number of Channels....................................................................................................... 1045

14.1.2 Register Base Addresses............................................................................................... 1046

14.1.3 Clock Supply................................................................................................................... 1047

14.1.4 Interrupt Requests and Error Notifications ..................................................................... 1048

14.1.5 Internal Input/Output Signals.......................................................................................... 1049

14.2 Overview................................................................................................................................... 1050

14.2.1 Block Diagram ................................................................................................................ 1050

14.2.2 Functional Overview....................................................................................................... 1051

14.3 Enabling CLMA......................................................................................................................... 1052

14.4 Functions .................................................................................................................................. 1053

14.4.1 Detection of Abnormal Clock Frequencies ..................................................................... 1053

14.4.2 Error Notification............................................................................................................. 1056

14.4.3 Self-Test ......................................................................................................................... 1056

14.5 Registers................................................................................................................................... 1057

14.5.1 Register Protection......................................................................................................... 1057

14.5.2 List of Registers.............................................................................................................. 1057

14.5.3 Reset of Registers.......................................................................................................... 1058

14.5.4 CLMATEST – Clock Monitor Test Register.................................................................... 1060

14.5.5 CLMATESTS – Clock Monitor Test Status Register ...................................................... 1062

14.5.6 CLMAnCTL – CLMAn Control Register.......................................................................... 1063

14.5.7 CLMAnCMPL – CLMAn Comparison Register L ........................................................... 1064

14.5.8 CLMAnCMPH – CLMAn Comparison Register H........................................................... 1065

14.5.9 CLMAKCPROT – Clock Monitor Register Key Code Protection Register...................... 1066

14.6 Operation.................................................................................................................................. 1067

14.6.1 Procedures to Enable CLMAn........................................................................................ 1067

14.6.2 Procedures to Reset by CLMATEST.RESCLM.............................................................. 1068

14.6.3 Procedures to do Self-Test ............................................................................................ 1069

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