S32K144参考手册：ARM Cortex-M4F核心模块解析

S32K144

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"S32K144参考手册，该手册详细介绍了Freescale Semiconductor公司生产的S32K144微控制器。" S32K144是一款基于ARMCortex-M4F核心的高性能微控制器，适用于各种工业和汽车应用。本参考手册旨在为开发者提供全面的技术信息，帮助他们理解和利用S32K144芯片的各种功能。章节1，关于本书： 1.1 目标读者：手册主要面向电子工程师、嵌入式系统开发者以及任何需要使用S32K144芯片进行产品设计和评估的专业人士。 1.2 组织结构：手册的结构清晰，包含多个章节，每个章节分别涵盖不同的组件和功能，便于用户按需查阅。 1.3 模块描述：书中提供了针对S32K144的特定信息，帮助解释各章节中的内容，并可能包含指向其他章节的相关链接。 1.3.1 示例：在同章内澄清芯片特定信息。 1.3.2 示例：指向不同章节的芯片特定信息引用。 1.4 寄存器描述：详细列出了S32K144中的所有寄存器，包括它们的功能、操作和访问方式。 1.5 公约：阐述了手册中使用的各种约定，如注释、警告和编号系统，以及符号表示法和特殊术语。章节2，介绍： 2.1 概览：概述了S32K144微控制器的基本特点和设计目标。 2.2 设备简介：详细介绍了S32K144的特性，包括其架构和设计理念。 2.3 功能概览：提供了一个功能亮点的总结，便于快速了解芯片的关键功能。 2.4 块图：通过图形化的方式展示了S32K144的内部模块布局，包括处理器、内存、外设等。 2.5 功能比较：可能包含了与其他微控制器的对比，以突出S32K144的独特优势。 2.6 模块功能类别：将芯片的各个模块分类，如ARMCortex-M4F核心模块，以及其他外设模块，如ADC、定时器、串行通信接口等。手册的其余部分可能会深入到每个模块的详细规格，包括中断系统、内存映射、电源管理、调试工具支持、外设接口、时钟和复位管理等。此外，还会提供编程模型、开发工具信息以及故障排查指南，以确保开发者能够顺利地在项目中集成和使用S32K144微控制器。

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Section number Title Page

24.1.2 EWM clocks...................................................................................................................................................425

24.1.3 EWM low-power modes................................................................................................................................ 425

24.1.4 EWM_out pin state in low power modes.......................................................................................................426

24.2 Introduction...................................................................................................................................................................426

24.2.1 Features.......................................................................................................................................................... 426

24.2.2 Modes of Operation....................................................................................................................................... 427

24.2.3 Block Diagram............................................................................................................................................... 428

24.3 EWM Signal Descriptions............................................................................................................................................ 429

24.4 Memory Map/Register Definition.................................................................................................................................429

24.4.1 EWM Register Descriptions.......................................................................................................................... 429

24.5 Functional Description..................................................................................................................................................434

24.5.1 The EWM_out Signal.................................................................................................................................... 434

24.5.2 The EWM_in Signal...................................................................................................................................... 435

24.5.3 EWM Counter................................................................................................................................................436

24.5.4 EWM Compare Registers.............................................................................................................................. 436

24.5.5 EWM Refresh Mechanism.............................................................................................................................436

24.5.6 EWM Interrupt...............................................................................................................................................437

24.5.7 Counter clock prescaler..................................................................................................................................437

Chapter 25

Error Injection Module (EIM)

25.1 Chip-specific EIM information.....................................................................................................................................439

25.1.1 EIM channels................................................................................................................................................. 439

25.1.2 EIM channel assignments.............................................................................................................................. 439

25.1.3 EIM_EICHDn_WORD register bit mapping.................................................................................................439

25.2 Introduction...................................................................................................................................................................440

25.2.1 Overview........................................................................................................................................................441

25.2.2 Features.......................................................................................................................................................... 442

25.3 Memory map and register definition.............................................................................................................................442

25.3.1 Error Injection Module Configuration Register (EIM_EIMCR)................................................................... 443

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25.3.2 Error Injection Channel Enable register (EIM_EICHEN).............................................................................444

25.3.3

Error Injection Channel Descriptor, Word0 (EIM_EICHDn_WORD0)....................................................... 445

25.3.4

Error Injection Channel Descriptor, Word1 (EIM_EICHDn_WORD1)....................................................... 446

25.4 Functional description...................................................................................................................................................446

Chapter 26

Error Reporting Module (ERM)

26.1 Chip-specific ERM information................................................................................................................................... 449

26.1.1 ERM memory channels..................................................................................................................................449

26.1.2 Sources of memory error events.................................................................................................................... 449

26.2 Introduction...................................................................................................................................................................450

26.2.1 Overview........................................................................................................................................................450

26.2.2 Features.......................................................................................................................................................... 450

26.3 Memory map and register definition.............................................................................................................................450

26.3.1 ERM Configuration Register (ERM_CR)......................................................................................................451

26.3.2 ERM Status Register (ERM_SR)...................................................................................................................453

26.3.3

ERM Memory n Error Address Register (ERM_EARn)...............................................................................454

26.4 Functional description...................................................................................................................................................455

26.4.1 Single-bit correction events........................................................................................................................... 455

26.4.2 Non-correctable error events..........................................................................................................................455

Chapter 27

Watchdog timer (WDOG)

27.1 Chip-specific Watchdog timer (WDOG) information.................................................................................................. 457

27.1.1 WDOG clocks................................................................................................................................................457

27.1.2 WDOG low-power modes............................................................................................................................. 457

27.2 Introduction...................................................................................................................................................................458

27.2.1 Features.......................................................................................................................................................... 458

27.2.2 Block diagram................................................................................................................................................459

27.3 Memory map and register definition.............................................................................................................................459

27.3.1 Watchdog Control and Status Register (WDOG_CS)................................................................................... 460

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27.3.2 Watchdog Counter Register (WDOG_CNT).................................................................................................462

27.3.3 Watchdog Timeout Value Register (WDOG_TOVAL)................................................................................ 463

27.3.4 Watchdog Window Register (WDOG_WIN)................................................................................................464

27.4 Functional description...................................................................................................................................................464

27.4.1 Watchdog refresh mechanism........................................................................................................................464

27.4.2 Configuring the Watchdog.............................................................................................................................466

27.4.3 Clock source...................................................................................................................................................468

27.4.4 Using interrupts to delay resets......................................................................................................................469

27.4.5 Backup reset...................................................................................................................................................469

27.4.6 Functionality in debug and low-power modes...............................................................................................470

27.4.7 Fast testing of the watchdog...........................................................................................................................470

Chapter 28

System Clock Generator (SCG)

28.1 Chip-specific System Clock Generator (SCG) information......................................................................................... 473

28.1.1 Information of SCG on this device................................................................................................................ 473

28.2 Introduction...................................................................................................................................................................473

28.2.1 Features.......................................................................................................................................................... 473

28.3 Memory Map/Register Definition.................................................................................................................................475

28.3.1 Version ID Register (SCG_VERID)..............................................................................................................476

28.3.2 Parameter Register (SCG_PARAM)............................................................................................................. 476

28.3.3 Clock Status Register (SCG_CSR)................................................................................................................477

28.3.4 Run Clock Control Register (SCG_RCCR)...................................................................................................480

28.3.5 VLPR Clock Control Register (SCG_VCCR)...............................................................................................482

28.3.6 HSRUN Clock Control Register (SCG_HCCR)............................................................................................485

28.3.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG).................................................................487

28.3.8 System OSC Control Status Register (SCG_SOSCCSR)..............................................................................488

28.3.9 System OSC Divide Register (SCG_SOSCDIV).......................................................................................... 490

28.3.10 System Oscillator Configuration Register (SCG_SOSCCFG)......................................................................491

28.3.11 Slow IRC Control Status Register (SCG_SIRCCSR)....................................................................................493

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28.3.12 Slow IRC Divide Register (SCG_SIRCDIV)................................................................................................494

28.3.13 Slow IRC Configuration Register (SCG_SIRCCFG)....................................................................................495

28.3.14 Fast IRC Control Status Register (SCG_FIRCCSR).....................................................................................496

28.3.15 Fast IRC Divide Register (SCG_FIRCDIV)..................................................................................................498

28.3.16 Fast IRC Configuration Register (SCG_FIRCCFG)..................................................................................... 499

28.3.17 Fast IRC Trim Configuration Register (SCG_FIRCTCFG)..........................................................................499

28.3.18 Fast IRC Status Register (SCG_FIRCSTAT)................................................................................................501

28.3.19 System PLL Control Status Register (SCG_SPLLCSR)...............................................................................502

28.3.20 System PLL Divide Register (SCG_SPLLDIV)............................................................................................504

28.3.21 System PLL Configuration Register (SCG_SPLLCFG)............................................................................... 505

28.4 Functional description...................................................................................................................................................506

28.4.1 SCG Clock Mode Transitions........................................................................................................................506

Chapter 29

Peripheral Clock Controller (PCC)

29.1 Introduction...................................................................................................................................................................511

29.2 Features.........................................................................................................................................................................511

29.3 Functional description...................................................................................................................................................512

29.4 Memory map and register definition.............................................................................................................................512

29.5 PCC Register Descriptions........................................................................................................................................... 512

29.5.1 PCC Memory Map.........................................................................................................................................512

29.5.2 PCC DMA (PCC_DMA)............................................................................................................................... 513

29.5.3 PCC MPU (PCC_MPU).................................................................................................................................515

29.5.4 PCC Flash (PCC_Flash).................................................................................................................................516

29.5.5 PCC DMA_channel_mutiplexer (PCC_DMA_channel_mutiplexer)............................................................518

29.5.6 PCC FlexCAN_0 (PCC_FlexCAN_0)...........................................................................................................519

29.5.7 PCC FlexCAN_1 (PCC_FlexCAN_1)...........................................................................................................520

29.5.8 PCC FTM_3 (PCC_FTM_3)......................................................................................................................... 522

29.5.9 PCC ADC_1 (PCC_ADC_1).........................................................................................................................523

29.5.10 PCC FlexCAN_2 (PCC_FlexCAN_2)...........................................................................................................525

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29.5.11 PCC LPSPI_0 (PCC_LPSPI_0).....................................................................................................................526

29.5.12 PCC LPSPI_1 (PCC_LPSPI_1).....................................................................................................................528

29.5.13 PCC LPSPI_2 (PCC_LPSPI_2).....................................................................................................................529

29.5.14 PCC PDB1 (PCC_PDB1).............................................................................................................................. 531

29.5.15 PCC CRC (PCC_CRC)..................................................................................................................................532

29.5.16 PCC PDB0 (PCC_PDB0).............................................................................................................................. 534

29.5.17 PCC LPIT0 (PCC_LPIT0).............................................................................................................................535

29.5.18 PCC FTM0 (PCC_FTM0)............................................................................................................................. 536

29.5.19 PCC FTM1 (PCC_FTM1)............................................................................................................................. 538

29.5.20 PCC FTM2 (PCC_FTM2)............................................................................................................................. 539

29.5.21 PCC ADC0 (PCC_ADC0).............................................................................................................................541

29.5.22 PCC RTC (PCC_RTC).................................................................................................................................. 542

29.5.23 PCC LPTMR0 (PCC_LPTMR0)................................................................................................................... 544

29.5.24 PCC (PCC_)...................................................................................................................................................546

29.5.25 PCC PORTA (PCC_PORTA)........................................................................................................................547

29.5.26 PCC PORTB (PCC_PORTB)........................................................................................................................549

29.5.27 PCC PORTC (PCC_PORTC)........................................................................................................................550

29.5.28 PCC PORTD (PCC_PORTD)........................................................................................................................551

29.5.29 PCC PORTE (PCC_PORTE).........................................................................................................................553

29.5.30 PCC FlexIO (PCC_FlexIO)........................................................................................................................... 554

29.5.31 PCC EWM (PCC_EWM).............................................................................................................................. 555

29.5.32 PCC LPI2C0 (PCC_LPI2C0).........................................................................................................................557

29.5.33 PCC LPUART0 (PCC_LPUART0)...............................................................................................................558

29.5.34 PCC LPUART1 (PCC_LPUART1)...............................................................................................................560

29.5.35 PCC LPUART2 (PCC_LPUART2)...............................................................................................................561

29.5.36 PCC CMP0 (PCC_CMP0).............................................................................................................................563

Chapter 30

Local Memory Controller (LMEM)

30.1 Introduction...................................................................................................................................................................565

S32K144 Reference Manual, Rev. 1 Draft H, 02/2016

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