AS3911 NFC Initiator/Reader IC Datasheet: High-Performance, Flexible & Low-Power Solution

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AS3911是一款由奥地利微电子公司（Austriamicrosystems）设计的高性能集成NFC发起器/高频（HF）读卡器集成电路，其官方文档是AS3911_NDADatasheet_EN_v3.pdf。该芯片的主要特性如下： 1. **综合功能**：AS3911集成了模拟前端（AFE）和高度集成的数据帧系统，支持ISO 18092（NFC IP-1）发起者模式、ISO 18092 NFC IP-1活动目标模式，以及ISO 14443A和B协议（包括高速率）和FeliCa™读取功能。它还支持定制协议的实现，允许在外部微控制器上进行流式传输和透明模式的数据处理。 2. **针对基础设施应用**：与专为移动电话设计的NFC设备相比，AS3911更适合于基础设施侧的NFC系统，因为它注重优化射频性能、灵活性和低功耗。这意味着它非常适合那些需要稳定且能适应各种应用场景的环境。 3. **自动天线调谐技术**：奥地利微电子公司的独特自动天线调谐技术使得AS3911特别适合使用直接驱动天线的应用。这是其区别于其他高频读卡器集成电路的一个关键优势，它包含两个差分低阻抗（1Ω）的天线驱动器，提高了信号传输的效率。 4. **灵活性与兼容性**：AS3911内置的AFE和数据帧系统提供了很高的可扩展性，允许用户根据需要配置和实施不同的通信协议，这增加了其在不同应用场景下的适应性。 5. **低功耗设计**：考虑到基础设施应用通常对能耗有严格的要求，AS3911在保持高性能的同时，注重了功耗的优化，确保在长时间运行下仍能保持高效。总结来说，AS3911是一款多功能且高度集成的NFC解决方案，特别适用于对射频性能、灵活性和低功耗有高需求的基础设施应用，如门禁系统、支付终端或物联网设备等。其内置的技术和特性使其在竞争激烈的NFC市场中脱颖而出，为用户提供了一站式的NFC解决方案。

www.austriamicrosystems.com/3911 Revision 1.1 14 - 86

AS3911

Datasheet - Detailed Description

7.1 Transmitter

Transmitter incorporates drivers which drive external antenna through pins RFO1 and RFO2. Single sided and differential driving is possible. The

transmitter block additionally contains a sub-block which modulates transmitted signal (OOK or configurable AM modulation).

The AS3911 transmitter is indented to directly drive antennas (without 50

 cable, usually antenna is on the same PCB). Operation with 50

cable is also possible, but in that case some of the advanced features are not possible.

7.2 Receiver

The receiver detects transponder modulation superimposed on the 13.56MHz carrier signal. The receiver contains two receive chains (one for

AM and another for PM demodulation) which are composed of a peak detector followed by two gain and filtering stages and a final digitizer

stage. The filter characteristics are adjusted to optimize performance over different ISO modes and bit rates (sub-carrier frequencies from 212

kHz to 6.8 MHz are supported). The receiver chain inputs are RFI1 and RFI2 pins; output of digitizer stage is demodulated sub-carrier signal.

The receiver chain incorporates several features which enable reliable operation in challenging phase and noise conditions.

7.3 Phase and Amplitude Detector

The phase detector is observing the phase difference between the transmitter output signals (RFO1 and RFO2) and the input signals RFI1 and

RFI2. Signals RFI1 and RFI2 are proportional to the signal on the antenna LC tank. RFI1 and RFI2 signals are also used to run the self-mixer

which generates output proportional to their amplitude. The phase detector and self-mixer blocks are used for several purposes:

PM demodulation by observing RFI1 and RFI2 phase variation (LF signal is fed to the Receiver)

Average phase difference between RFOx pins and RFIx pins is used to check antenna tuning

Output of mixer is used to measure amplitude of signal present on pins RFI1 and RFI2.

7.4 A/D Converter

The AS3911 contains a built in A/D Converter. Its input can be multiplexed from different sources and is used in several applications

(measurement of RF amplitude and phase, calibration of modulation depth…..). The result of A/D conversion is stored in a register which can be

read through the SPI interface.

7.5 Capacitive Sensor

Capacitive sensor is used to implement low power detection of transponder presence. Capacitive sensor performs measurement of capacitance

between its two electrodes. Presence of an object (card, hand) changes the capacitance. During calibration the reference capacitance, which

represents parasitic capacitance of environment is stored. In normal operation capacitance is periodically measured and compared to stored

reference value. When the measured capacitance is larger than stored reference value (threshold value can be defined in a register) an interrupt

is sent to external controller.

7.6 External Field Detector

The External Field Detector is a low power block which is used in NFC mode to detect presence of external RF field. It supports two different

detection thresholds, Peer Detection Threshold and Collision Avoidance Threshold. Peer Detection Threshold is used in the NFCIP target mode

to detect presence of initiator field. It is also used in active communication initiator mode to detect activation of target field. Collision Avoidance

Threshold is used to detect a presence of RF field during NFCIP Collision Avoidance procedure.

7.7 Quartz Crystal Oscillator

The quartz crystal oscillator can operate with 13.56MHz and 27.12MHz crystals. At start-up the transconductance of the oscillator is increased to

achieve fast start-up. Since the start-up time varies depending on crystal type, temperature and other parameters, the oscillator amplitude is

observed and an interrupt is sent when stable operation is reached to inform the controller that the clock signal is stable and reader field can be

switched on. The use of 27.12 MHz crystal is mandatory in case VHBR framing is used.

It also provides a clock signal to the external microcontroller (MCU_CLK) according to setting in the control register.

www.austriamicrosystems.com/3911 Revision 1.1 15 - 86

AS3911

Datasheet - Detailed Description

7.8 Power Supply Regulators

Integrated power supply regulators ensure high power supply rejection of a complete reader system. In case PSRR of the reader system has to

be improved, the command

Adjust Regulators

is sent. As result of this command, the power supply level of VDD is measured in maximum load

conditions and the regulated voltage reference is set 250mV below this measured level to assure a stable regulated supply. The resulting

regulated voltage is stored in a register. It is also possible to define regulated voltage by writing a configuration register. In order to decouple any

noise sources from different parts of IC there are three regulators integrated with separated external blocking capacitors (regulated voltage of all

is the same in 3.3 V supply mode). One regulator is for the analog blocks, one for digital blocks, there is also a separate one for the antenna

drivers. In case of low cost applications some (or all) regulators may not be used to save on external components.

This block additionally generates a reference voltage for the analog processing (AGD - analog ground). This voltage also has an associated

external buffer capacitor.

7.9 POR and Bias

This block contains the bias current and voltage generator which provides bias currents and reference voltages to all other blocks. It also

incorporates a Power on Reset (POR) circuit which provides a reset at power-up and at low supply levels.

7.10 RC Oscillator and Wake-up Timer

The AS3911 includes several possibilities of low power detection of a card presence (capacitive sensor, phase measurement, amplitude

measurement). RC oscillator and register configurable Wake-up timer are used to schedule periodic detection. When presence of a card is

detected an interrupt is sent to controller.

7.11 ISO14443 and NFCIP Framing

This block performs framing for receive and transmit according to the selected ISO mode and bit rate settings.

In reception it takes demodulated sub-carrier signal from Receiver. It recognizes the SOF, EOF and data bits, performs parity and CRC check,

organizes the received data in bytes and places them in the FIFO.

During transmit, it operates inversely, it takes bytes from FIFO, generates parity and CRC bits, adds SOF and EOF and performs final encoding

before passing modulation signal to transmitter.

In Transparent mode, the framing and FIFO are bypassed, the digitized sub-carrier signal, which is Receiver output, is directly sent to MISO pin,

signal applied to MOSI pin is directly used to modulate the transmitter.

7.12 FIFO

The AS3911 contains a 96 byte FIFO. Depending on the mode, it contains either data which has been received or data which is to be

transmitted.

7.13 Control Logic

The control logic contains I/O registers which define operation of device.

7.14 SPI Interface

A 4-wire Serial Peripheral Interface (SPI) is used for communication between external microcontroller and the AS3911.

www.austriamicrosystems.com/3911 Revision 1.1 16 - 86

AS3911

Datasheet - Application Information

8 Application Information

8.1 Operating Modes

The AS3911 operating mode is defined by the content of the

Operation Control Register

At power-up all bits of the

Operation Control Register

are set to 0, the AS3911 is in Power-down mode. In this mode AFE static power

consumption is minimized, only the POR and part of the bias are active, the regulators are transparent and are not operating. The SPI is still

functional in this mode so all settings of ISO mode definition and configuration registers can be done.

Control bit

en (bit 7 of the

Operation Control Register

) is controlling the quartz crystal oscillator and regulators. When this bit is set, the

device enters in Ready mode. In this mode the quartz crystal oscillator and regulators are enabled. An interrupt is sent to inform the

microcontroller when the oscillator frequency is stable.

Enable of Receiver and Transmitter are separated so it is possible to operate one without switching on the other (control bits

rx_en and tx_en). In

some cases this may be useful, in case the reader field has to be maintained and there is no transponder response expected receiver can be

switched-off to save current. Another example is NFCIP receive mode in which RF field is generated by the initiator and only Receiver operates.

Asserting the

Operation Control Register

bit wu while the other bits are set to 0 puts the AS3911 into the Wake-up mode which is used to

perform low power detection of card presence. In this mode the low power RC oscillator and register configurable Wake-up timer are used to

schedule periodic measurement(s). When a difference to the predefined reference is detected an interrupt is sent to wake-up the micro.

Capacitive sensor, phase measurement and amplitude measurement are available.

8.2 Transmitter

The Transmitter contains two identical push-pull driver blocks connected to the pins RFO1 and RFO2. These drivers are differentially driving

external antenna LC tank. It is also possible to operate only one of the two drivers by setting the

IO Configuration Register 1

bit single.

Each driver is composed of 8 segments having binary weighted output resistance. The MSB segment typical ON resistance is 2

, when all

segments are turned on; the output resistance is typically 1

. Usually all segments are turned on to define the normal transmission (non-

modulated) level. It is also possible to switch off certain segments when driving the non-modulated level to reduce the amplitude of signal on the

antenna and/or to reduce the antenna Q factor without making any hardware changes. The

RFO Normal Level Definition Register

defines which segments are turned on to define the normal transmission (non-modulated) level. Default setting is that all segments are turned

on.

Using the single driver mode the number and therefore the cost of the antenna LC tank components is halved, but also the output power is

reduced. In single mode it possible to connect two antenna LC tanks to the two RFO outputs and multiplex between them by controlling the

Configuration Register 1

bit rfo2.

In order to transmit the data the transmitter output level needs to be modulated. The AM and OOK modulation are supported. The type of

modulation is defined by setting the bit

tr_am in the

Auxiliary Definition Register

. For the operation modes supported by the AS3911

framing the setting of modulation type is done automatically by sending direct command

Analog Preset

During the OOK modulation (for example ISO14443A) the Transmitter drivers stop driving the carrier frequency; drivers are frozen in state before

the modulation. As consequence the amplitude of the antenna LC tank oscillation decays, the time constant of the decay is defined with the LC

tank Q factor. The decay time in case of OOK modulation can be shortened by asserting the

Auxiliary Definition Register

bit ook_hr. When

this bit is set to logic one the drivers are put in tristate during the OOK modulation.

AM modulation (for example ISO14443B) is done by increasing the output driver impedance during the modulation time. This is done by

reducing the number of driver segments which are turned on. The AM modulated level can be automatically adjusted to the target modulation

depth by defining the target modulation depth in the

AM Modulation Depth Control Register

and sending the

Calibrate Modulation

Depth

direct command. Please refer to the chapter on AM Modulation Depth: Definition and Calibration for further details.

www.austriamicrosystems.com/3911 Revision 1.1 17 - 86

AS3911

Datasheet - Application Information

8.2.1 Slow Transmitter Ramping

When transmitter is enabled it starts to drive the antenna LC tank with full power, the ramping of field emitted by antenna is defined by antenna

LC tank Q factor.

However there are some reader systems where the reader field has to transition with a longer transition time when it is enabled. The STIF

(Syndicat des transports d'Ile de France) specification requires a transition time from 10% to 90% of field longer than or equal to 10µs.

The AS3911 supports that feature. It is realized by collapsing VSP_RF regulated voltage when transmitter is disabled and ramping it when

transmitter is enabled. Typical transition time is 15µs at 3V supply and 20µs at 5V supply.

Procedure to implement the slow transition:

When transmitter is disabled set

IO Configuration Register 2

bit slow_up to 1. Keep this state at least 2ms to allow discharge of

VSP_RF.

Enable transmitter, its output will ramp slowly

Before sending any command set the bit slow_up back to 0.

8.3 Receiver

The receiver performs demodulation of the transponder sub-carrier modulation which is superimposed on the 13.56 MHz carrier frequency. It

performs AM and/or PM demodulation, amplification, band-pass filtering and digitalization of sub-carrier signals. Additionally it performs RSSI

measurement, automatic gain control (AGC) and Squelch function.

Receiver comprises two complete receive channels for AM demodulation and PM demodulation. In case both channels are active the selection

of channel used for reception framing is done automatically by receive framing logic. The receiver is switched on when

Operation Control

bit rx_en is set to one. Additionally the

Operation Control Register

contains bits rx_chn and rx_man, rx_chn defines whether

both, AM and PM, demodulation channels will be active or only one of them, while bit

rx_man defines the channel selection mode in case both

channels are active (automatic or manual). Operation of the Receiver is controlled by four Receiver Configuration registers.

The operation of the receiver is additionally controlled by the signal

rx_on which is set high when modulated signal is expected on the receiver

input. This signal is used to control RSSI and AGC and also enables processing of receiver output by Framing logic. Signal

rx_on is

automatically set high after Mask Receive timer expires. Signal

rx_on can also be directly controlled by the controller by sending direct

commands

Mask Receive Data

and

Unmask Receive Data

. Figure 5 illustrates the Receiver block diagram.

8.3.1 Demodulation Stage

First stage performs demodulation of transponder sub-carrier response signal, which is superimposed on HF field carrier. Two different blocks

are implemented for AM demodulation: Peak Detector and AM demodulator mixer. The choice of the demodulator, which is used, is made by the

Receiver Configuration Register 1

bit amd_sel.

Peak detector performs AM demodulation using peak follower. Both, the positive and negative peaks are tracked to suppress common mode

signal. It is limited in speed; it can operate for sub-carrier frequencies up to fc/8 (1700kHz). It has demodulation gain G = 0.7. Its input is taken

from one demodulator input only (usually RFI1).

AM demodulator mixer uses synchronous rectification of both receiver inputs (RFI1 and RFI2). Its gain is G = 0.55. Mixer demodulator is

optimized for VHBR sub-carrier frequencies. (fc/8 and higher). For sub-carrier frequency fc/8 (1700kHz) both peak follower and mixer can be

used, while for fc/4 and fc/2 are supported only by mixer.

By default the Peak detector is used, for data rates fc/8 and higher use of mixer is automatically preset by sending direct command

Analog

Preset

PM demodulation is also done by a mixer. The PM demodulator mixer has differential outputs with 60mV differential signal for 1% phase change

(16.67mV per degree). Its operation is optimized for sub-carrier frequencies up to fc/8 (1700 kHz).

In case the demodulation is done externally of the AS3911 it is possible to multiplex the LF signals applied to pins RFI1 and RFI2 directly to the

gain and filtering stage by selecting the

Receiver Configuration Register 2

bit lf_en.

www.austriamicrosystems.com/3911 Revision 1.1 18 - 86

AS3911

Datasheet - Application Information

Figure 5. Receiver Block Diagram

8.3.2 Filtering and Gain Stages

The receiver chain has band pass filtering characteristics. Filtering is optimized to pass sub-carrier frequencies while rejecting carrier frequency

and low frequency noise and DC component. Filtering and gain is implemented in three stages where the first and the last stage have the first

order high pass characteristics, while the mid stage has second order low pass characteristic.

Gain and filtering characteristics can be optimized for current application by writing the

Receiver Configuration Register 1

(filtering),

Receiver Configuration Register 3

(gain in first stage) and

Receiver Configuration Register 4

(gain in second and third stage).

Gain of first stage is about 20dB and can be reduced in six 2.5dB steps. There is also a special boost mode available, which boosts the

maximum gain for additional 5.5 dB. In case of VHBR (fc/8 and fc/4) the gain is lower. The first stage gain can only be modified by writing

Receiver Configuration Register 3

. The default setting of this register is the minimum gain. Default first stage zero is located at 60 kHz, it

can also be lowered to 40kHz or 12kHz by writing option bits in the

Receiver Configuration Register 1

. The control of the first and third

stage zeros is done with common control bits (see Table 8)

Gain in the second and third stage is 23dB and can be reduced in six 3dB steps. Gain of these two stages is included in AGC and Squelch loops

or can be manually set in

Receiver Configuration Register 4

. Sending of direct command

Reset Rx Gain

is necessary to initialize the

AGC, Squelch and RSSI block. Sending this command clears the current Squelch setting and loads the manual gain reduction from

Receiver

Configuration Register 4

. Second stage has a second order low pass filtering characteristic, the pass band is adjusted according to sub-

carrier frequency using the bits lp2 to lp0 of the

Receiver Configuration Register 1

. See Table 7 for -1dB cut-off frequency for different

settings.

Table 7. Low Pass Control

rec1<5> lp2 rec1<4> lp1 rec1<3> lp0 -1 dB point

0 0 0 1200 kHz

0 0 1 600 kHz

0 1 0 300 kHz

10 02 MHz

10 17 MHz

Other Not used

digital

sub-carrier

Demodulator

Mixer

Peak Detector

AGC

Squelch

RSSI

rec4<7:4>

AGC

Squelch

RSSI

rec4<3:0>

rec3<7:5>

rec3<4:2>

rec3<2:0> rec1<5:3>

digital

sub-carrier

AC coupling

+ 1

gain stage

Low-pass

+ 2

gain stage

High-pass

+ 3

gain stage

Digitizing

stage

Demodulation

stage

Demodulator

Mixer

rec1<7:6>

rec2<6:5>

RF_IN1

RF_IN2

RSSI_AM<3:0>

RSSI_PM<3:0>

RX_on

sg_on

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