"7系FPGA移植用户手册更新与方法指南"

需积分: 5 199 浏览量更新于2023-12-09 收藏 564KB PDF 举报

The 7 Series FPGA Migration Methodology Guide, also known as UG429, is a comprehensive manual for users looking to migrate their designs to 7 Series FPGAs. This guide, last updated on April 4, 2018, provides a detailed methodology for the migration process and includes revision history, feedback options, and a thorough overview of the migration process. The manual covers a variety of topics related to migrating designs to 7 Series FPGAs, such as updated PCIe interfaces, STARTUP_VIRTEX6 considerations, clocking components, and FIFO descriptions. It is designed to provide users with the necessary information and guidelines to successfully transition their designs to 7 Series FPGAs. The revision history of the guide indicates the updates made in different versions, such as the inclusion of clocking components paragraph, description updates of FIFO18E1/FIFO36E1, and other relevant changes. This demonstrates the commitment to providing users with up-to-date and accurate information. The feedback option included in the manual allows users to provide their input and suggestions, highlighting the importance of user input and continuous improvement. This indicates that Xilinx is dedicated to providing a user-focused experience and is open to feedback for future updates. Overall, the 7 Series FPGA Migration Methodology Guide is a valuable resource for users looking to migrate their designs to 7 Series FPGAs. It provides a comprehensive methodology, up-to-date information, and a mechanism for user feedback, making it an essential tool for successful migration processes.

7 Series FPGAs Migration 6

UG429 (v1.2) April 04, 2018

www.xilinx.com

Chapter 1: Targeting/Retargeting Considerations for 7 Series Devices

List of register instances with set and reset:

My_async_reg

If any of these warnings are encountered, it is suggested to evaluate the code for changes

that can eliminate the need for describing both a asynchronous set and reset condition.

Many engineers use the inherent initialization of registers and latches in the FPGA via the

global set/reset (GSR) signal by implicitly specifying initialization of an inferred register,

thus creating a more robust and sometimes smaller circuit. With initialization, a different

start-up state from reset state is allowed, which in some cases (such as a state machine with

certain states that must be run at start-up but perhaps not on a subsequent reset) it

consumes less logic than an uninitialized state yields. Initialization also allows for the RTL

description to more closely and accurately behave as the actual FPGA, creating a more

accurate representation of the circuit. For this reason it is suggested to use register

initialization on any inferred register, SRL, or RAM when possible.

In this code example, the reg register is initialized with the value of 1:

signal reg: std_logic := '1';

...

process (clk) begin

if (clk'event and clk='1') then

if (rst='1') then

reg <= '0';

else

reg <= val;

end if;

end process;

In the coding example, the use of initialization eliminates the need to specify a set

condition for the sole purpose of creating an initial condition of a logic one. Even if the

initial condition matches the reset condition, it is still suggested to specify register

initialization to allow the simulation start-up state to more accurately reflect the initial

condition of the FPGA without requiring a reset condition.

Limit Use of Active-Low Control Signals

It is not recommended to use inferred or instantiated components with active-Low control

signals due to the combination of:

• The 7 series device’s coarse slice composition (8 registers per slice).

• The absence of a programmable inversion element on the slice control signals in the

7 series device.

• Hierarchical design methods that do not allow optimization across hierarchical

boundaries, such as the use of KEEP_HIERARCHY, partitions, partial reconfiguration, or

bottom-up synthesis.

Send Feedback

剩余26页未读，继续阅读

独行者笃行

粉丝: 0
资源: 5

"7系FPGA移植用户手册更新与方法指南"

7系列FPGA手册

FPGA用户手册

7系列FPGA 配置用户手册

Xilinx 7系列FPGA移植适配使用手册指南

7Series_Migration_fpga_XILINX7_migration_移植_xilinx手册_

在FPGA上成功移植蜂鸟E203

Cortex-M3系统个性详解：Kintex-7 FPGA开发板用户手册

μCOS-Ⅱ中文手册_fpga_state1tu_

基于FPGA的贪吃蛇

FPGA2ASIC CONVERSION REFERENCE MANUAL

最新资源