"IEC 60068-2-82-2019: 新版电子锡须试验标准发布"

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本文将对IEC 60068-2-82-2019功率电子锡须试验标准进行详细分析和总结。IEC 60068-2-82是国际电工委员会（IEC）制定的环境测试标准之一，主要用于测试电子组件和部件中使用的锡须问题。本标准的全称为IEC 60068-2-82-2019 Environmental testing – Part 2-82: Tests – Test Xw1: Whisker test methods for components and parts used in electronic assemblies（环境测试-第2-82部分：试验-试验Xw1：电子组件和部件中使用的锡须测试方法）。该标准的最新版本为2019年发布的第2版。本标准的目的是确定用于检测电子组件和部件中锡须问题的测试方法。锡须是一种细小的金属纤维，可能生长在电子装置中的焊点或其他表面上。它们可能导致短路、断路或其他故障，从而影响电子设备的性能和可靠性。 IEC 60068-2-82的第一部分概述了测试方法的一般要求，包括试样的准备、测试设备的选择、测试条件的确定等。该部分还介绍了一些针对不同类型电子组件和部件的特殊要求和注意事项。这些要求和注意事项有助于确保测试的准确性和可重复性。第二部分详细描述了锡须测试的具体方法。测试方法主要包括两个方面：一是在常温条件下对试样进行观察和分析，以检测锡须的存在和数量；二是在加速寿命测试中，通过模拟环境应力（如温度、湿度、振动等）来促进锡须的生长和发展。这些方法可以帮助制造商在实际使用环境下评估电子组件和部件的抗锡须性能。 IEC 60068-2-82标准的应用范围涵盖了多种不同类型的电子组件和部件，包括集成电路、电容器、电感器、连接器等。该标准适用于电子设备制造商、电子组件供应商和相关测试实验室等。总之，IEC 60068-2-82-2019是一项重要的环境测试标准，旨在帮助电子设备制造商评估和改善电子组件和部件的抗锡须性能。该标准提供了一套可靠的测试方法，可以有效地检测和评估锡须问题，从而提高电子设备的可靠性和性能。制造商和供应商可以依靠该标准来确保其产品符合质量和可靠性要求，从而为用户提供更好的使用体验。同时，该标准也为测试实验室提供了参考，以确保测试的标准化和一致性。

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– 10 – IEC 60068-2-82:2019 © IEC 2019

– parts shall be firmly attached on the fixture when the jig is tilted.

Care shall be taken to avoid whiskers breaking off while attaching the specimen to, and

handling the specimen with, the fixture jig.

5 Preparation for test

5.1 Selection of relevant tests

5.1.1 General

The samples shall represent finished (final) products as supplied to the customer (including

sub-process steps like trim and form, brushing, post-plating). The appropriate test methods

shall be selected according to the decision tree given in Figure 2.

– 12 – IEC 60068-2-82:2019 © IEC 2019

5.1.3 Pre-aging (storage in the supply chain) before testing

Different manufacturing processes and different manufacturing routes require adapted pre-

aging times. The storage time prior to submitting specimens to preconditioning and testing

shall be at least 30 days, but not longer than 120 days after tin (alloy) plating.

5.2 Handling of the specimens

It is recommended that specimens be handled with a fixing jig as specified in 4.6 to prevent

contamination. Wherever possible, the fixing jig should not make contact with the metallic

surfaces of the specimens. However, contamination inherent to the production process and

the pre-conditioning shall not be removed (e.g. residues from plating or soldering, such as

flux residues).

The

specimens shall be handled carefully to prevent whiskers from breaking off unexpectedly.

For required intermediate results reporting, already identified and broken whiskers (e.g. by

handling) shall be recorded in the final report (see Clause 10).

5.3 Sample size

The following minimum sample size shall be adopted for each test condition and for each kind

of preconditioning, unless other sample sizes are prescribed by the relevant specification.

Sample sizes for tests:

• All pins from 40 components with pin count per component < 4 pins.

• All pins from 20 components with pin count per component ≥ 4 pins and < 20 pins.

• All pins from 10 components with pin count per component ≥ 20 pins and < 40 pins.

• All pins from 5 components with pin count per component ≥ 40 pins, but not more than 400

pins.

• For mechanical parts like ESD protection shields, mechanical fixtures: ≥ 10 parts, up to an

area of 25 cm

• For press-fit applications: ≥ 200 single pins.

• For all other parts like jumpers, wires, parts for electrical connections, male multipoint

connectors: ≥ 80 parts.

• For strip/belt galvanic: 25 cm

or minimum 30 cm taken from the start and the end of the

coil.

The sample size applies to specimens with or without heat treatment in accordance with 5.5

and 5.6 and to each test condition selected from 5.1.

Similarity rules as given in 7.2 may be employed for the selection of samples.

5.4 Surface and base materials for test selection

Table 1 summarizes material systems recognized for their effective whisker mitigation, for

which certain test conditions may be omitted (see Figure 2 and Annex D). The technical

background for the omission of certain test conditions is briefly discussed in Annex D

Table 1 applies to:

– copper-based base materials;

– ceramic-based materials;

– Fe and FeNi alloy base materials;

IEC 60068-2-82:2019 © IEC 2019 – 13 –

– other base materials which are covered with by a continuous Cu underlayer (those shall

be treated as 'Cu alloy' in Table 1), with the exception of CuZn alloys. If a CuZn alloy is

used, an Ni underlayer (0,5 µm to 4 µm) not exhibiting voids or cracks is required.

Table 1 – Material systems recognized for effective whisker mitigation

Part Sn finish layer Top

underlayer

Base

material

Post-treatment

Electronic

components

Solder area of

electro-

mechanic

components

such as

connectors,

shieldings, etc.

Galvanic matt

(Carbon content in the

finish < 150 parts per

million in weight. Target

value, measured minimum

2 µm below the surface).

Minimum

3 µm Sn

Galvanic Ni

0,5 µm to

4 µm

Cu alloy

No post-

treatment

Galvanic Ni

2 µm to

15 µm

Ceramic, Fe

and FeNi

alloy

Minimum

3 µm Sn

Cu alloy

Reflow process

Ceramic, Fe

and FeNi

alloy

No post-

treatment

Minimum

7 µm Sn

Cu alloy

Annealing

Ceramic, Fe

and FeNi

alloy

No post-

treatment

Galvanic Ni

1 µm to 3 µm

Cu alloy

No post-

treatment

Hot dip plating of

Sn/SnAg/SnAgCu/SnCu0,7

Minimum

3 µm Sn

Cu alloy

No post-

treatment

Ceramic, Fe

and FeNi

alloy

Galvanic Ni

1 µm to 3 µm

Cu alloy

Other Sn alloys not covered by Table 1 may be used, but for these alloys, the ambient test cannot be omitted.

Concerning the effectiveness of whisker mitigation, the use of galvanic matt Sn alloy finishes is currently under

discussion. In particular, the following alloying elements are considered: Ag, Bi, Cu and Pb.

The Sn finish shall melt during the reflow process (e.g. > 10 s at 235 °C), without exhibiting discoloration or

de-wetting.

Annealing shall take place within 24 h after plating for at least one hour at a temperature of 150 °C or

comparable conditions (e.g. 10 min at a temperature of 180 °C).

Ni-layer shall not exhibit voids or cracks (ductile Ni).

The post-treatment shall establish a homogeneous layer of Cu

and/or Cu

Sn with a thickness of at least

0,5 µm.

The temperature-cycling test of 6.4 may be omitted if the CTE mismatch (∆CTE) (see 3.3) is

less than 8 × 10

−6

/K. The test conditions and the selection of test methods do not depend on

the presence of any underlayer system (e.g. Ni, Cu).

5.5 Preconditioning of test specimen not intended for soldering/welding

5.5.1 Preconditioning of test specimen intended for press-fit applications

Unless otherwise specified by the relevant specification, press-fit pins shall be inserted into a

plated through-hole of a laminated circuit board consisting of copper-clad epoxy woven

E-glass (for example, in accordance with IEC 61249-2-7, IEC 61249-2-35 or IEC 61249-2-22)

with the appropriate thickness and nominal finished hole diameter.

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