Nanya DDR3-4GB E-Die NT5CC256M16ER数据手册概述

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DDR3_NT5cc256M16er是一款由Nanya Technology Co., Ltd.提供的DDR3-4Gb（4GB）SDRAM芯片，其规格符合DDR3标准，具有先进的8n Prefetch Architecture。该芯片采用双数据速率（Double-datarate）设计，即在DQs、DQS和DM线上实现数据传输速度翻倍，以提高数据吞吐量。核心特性包括： 1. **数据完整性**：Nanya DDR3_NT5cc256M16er支持自动自刷新（ASR）功能，通过内置时钟（TS）进行控制，以确保在无操作期间内存的数据保持稳定。此外，提供自动刷新和自刷新模式，以便在低功耗情况下维护数据一致性。 2. **电源管理**： - **CAS Latency**：提供多种CAS latency选项，包括6/7/8/9/10/11/13/14级，用户可以根据应用需求选择适当的延迟时间。 - **CAS Write Latency**：支持5/6/7/8/9/10级写入延迟，允许灵活的性能调整。 - **Additive Latency**：提供了CL-0/CL-1/CL-2级别的附加延迟，进一步扩展了兼容性。 - **Write Recovery Time**：不同级别为5/6/7/8/10/12/14/16，根据需要控制数据恢复时间。 - **Burst Type**：支持顺序和交错burst模式，提高数据访问效率。 - **Burst Length**：支持BL8（8字节）和BC4（4字节）两种模式，同时可实现BC4or8onthefly，根据应用灵活选择。 3. **编程功能**：这款DDR3 SDRAM允许对某些参数进行配置，以适应不同的系统需求，但具体哪些参数可以编程并未在提供的部分中详述，需查阅完整的数据手册。 4. **电压兼容性**：1.35V DDR3L版本在1.5V DDR3设备中具有向后兼容性，这意味着它可以在更低的电压下运行，有利于降低功耗和散热。 5. **温度控制**：如果工作温度超过85°C，可能需要外部刷新以每3.9us一次，此时需要启用延长的SRT或ASR模式，以确保长期可靠运行。 Nanya DDR3_NT5cc256M16er是一款高性能、低功耗的DDR3内存芯片，适用于商业和工业应用，具备高级数据传输能力、多种工作模式以及可配置特性，以满足不同应用场景的需求。使用时务必参考数据手册中的详细指南和注意事项，确保正确地集成和优化系统性能。

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Version 1.2 16 Nanya Technology Cooperation ©

DDR3-4Gb E-Die

NT5CB(C)512M8EQ/NT5CB(C)256M16ER

MOD

Timing

CKE

MRS NOP NOP NOP NOPCMD

ADDR

tMOD

Non

MRS

VAL

Old Setting

Updating Setting

New Setting

VAL

Programming the Mode Registers (Cont’d)

The mode register contents can be changed using the same command and timing requirements during normal operation as

long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed

and CKE is high prior to writing into the mode register. The mode registers are divided into various fields depending on the

functionality and/or modes.

Mode Register MR0

The mode-register MR0 stores data for controlling various operating modes of DDR3 (L) SDRAM. It controls burst length,

read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which include

various vendor specific options to make DDR3(L) SDRAM useful for various applications. The mode register is written by

asserting low on , RA, A, WE, BA0, BA1, and BA2, while controlling the states of address pins according to the

following figure.

Version 1.2 18 Nanya Technology Cooperation ©

DDR3-4Gb E-Die

NT5CB(C)512M8EQ/NT5CB(C)256M16ER

Burst Length, Type, and Order

Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3

as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length,

burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4,

fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write

command via A12/.

Burst Type and Burst Order

Burst

Length

Read

Write

Starting

Column

Address

(A2,A1,A0)

Burst type:

Sequential

(decimal)

A3 = 0

Burst type:

Interleaved

(decimal)

A3 = 1

Note

Chop

Read

0,0,0

0,1,2,3,T,T,T,T

1,2,3

0,0,1

1,2,3,0,T,T,T,T

1,0,3,2,T,T,T,T

0,1,0

2,3,0,1,T,T,T,T

0,1,1

3,0,1,2,T,T,T,T

3,2,1,0,T,T,T,T

1,0,0

4,5,6,7,T,T,T,T

1,0,1

5,6,7,4,T,T,T,T

5,4,7,6,T,T,T,T

1,1,0

6,7,4,5,T,T,T,T

1,1,1

7,4,5,6,T,T,T,T

7,6,5,4,T,T,T,T

Write

0,V,V

0,1,2,3,X,X,X,X

1,2,4,5

1,V,V

4,5,6,7,X,X,X,X

Read

0,0,0

0,1,2,3,4,5,6,7

0,0,1

1,2,3,0,5,6,7,4

1,0,3,2,5,4,7,6

0,1,0

2,3,0,1,6,7,4,5

0,1,1

3,0,1,2,7,4,5,6

3,2,1,0,7,6,5,4

1,0,0

4,5,6,7,0,1,2,3

1,0,1

5,6,7,4,1,2,3,0

5,4,7,6,1,0,3,2

1,1,0

6,7,4,5,2,3,0,1

1,1,1

7,4,5,6,3,0,1,2

7,6,5,4,3,2,1,0

Write

V,V,V

0,1,2,3,4,5,6,7

2,4

Note:

1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than the BL8

mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected

on-the-fly via A12/, the internal write operation starts at the same point in time like a burst of 8 write operation. This means that

during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.

2. 0~7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst.

3. T: Output driver for data and strobes are in high impedance.

4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.

5. X: Do not Care.

DDR3-4Gb E-Die

NT5CB(C)512M8EQ/NT5CB(C)256M16ER

CAS Latency

The CAS Latency is defined by MR0 (bit A2, A4~A6) as shown in the MR0 Definition figure. CAS Latency is the delay, in

clock cycles, between the internal Read command and the availability of the first bit of output data. DDR3(L) SDRAM does

not support any half clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency

(CL); RL = AL + CL.

Test Mode

The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the MR0

definition figure. Programming bit A7 to a ‘1’ places the DDR3(L) SDRAM into a test mode that is only used by the DRAM

manufacturer and should not be used. No operations or functionality is guaranteed if A7=1.

DLL Reset

The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has been issued.

Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK

must be met before any functions that require the DLL can be used (i.e. Read commands or ODT synchronous

operations.)

Write Recovery

The programmed WR value MR0(bits A9, A10, and A11) is used for the auto precharge feature along with tRP to

determine tDAL WR (write recovery for auto-precharge)min in clock cycles is calculated by dividing tWR(ns) by tCK(ns)

and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be

equal or larger than tWR (min).

Precharge PD DLL

MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or ‘slow-exit’,

the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be

met prior to the next valid command. When MR0 (A12=1), or ‘fast-exit’, the DLL is maintained after entering precharge

power-down and upon exiting power-down requires tXP to be met prior to the next valid command.

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