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君正X2000 IoT应用处理器编程手册
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"君正X2000寄存器手册 X2000_PM_20210408.pdf"
本文档是君正X2000 IoT应用处理器的编程手册,详细介绍了这款基于MIPS32架构的芯片的寄存器配置和使用方法。该手册由Ingenic Semiconductor Co., Ltd.发布,旨在为开发者提供与Ingenic产品相关的技术资料,但并不授予任何Ingenic的知识产权许可。在使用该处理器时,用户需自行承担风险,Ingenic不对任何使用或潜在的知识产权侵权问题提供明示或暗示的保修。
X2000 IoT应用处理器是针对物联网应用设计的一款高性能芯片,可能包含一系列集成的功能,如CPU核心、内存控制器、外设接口等。由于其针对物联网应用,可能集成了低功耗管理单元,以适应长时间运行和节能的需求。手册中的寄存器描述是理解和控制处理器行为的关键,它们用于设置和读取处理器内部的状态和配置。
寄存器手册通常会涵盖以下几个方面:
1. **CPU寄存器**:包括通用寄存器、控制寄存器和状态寄存器,这些寄存器用于执行指令、管理中断和控制处理器的运行模式。
2. **内存管理寄存器**:用于配置内存映射、缓存控制和虚拟地址到物理地址的转换。
3. **外设接口寄存器**:每个外设都有自己的寄存器集,用于配置和控制其功能,如I/O端口、定时器、串行通信接口等。
4. **电源管理寄存器**:用于控制系统的睡眠模式、唤醒源和功耗优化。
5. **中断和异常处理**:寄存器用于管理和处理中断请求,以及异常情况,如故障和系统调用。
6. **调试和测试接口**:可能包括JTAG(联合测试行动组)或其他调试接口的寄存器,用于芯片的调试和故障排查。
由于内容未提供具体的寄存器细节,此处只能提供一般性的解释。实际的手册将详细列出每个寄存器的地址、位宽、每一位的含义以及如何操作它们。开发者在设计固件或驱动程序时,会依赖这些信息来正确地初始化和操作硬件。
在开发过程中,开发者需要仔细阅读手册,理解每个寄存器的作用,以确保软件与硬件的协同工作。同时,手册中可能还会包含一些警告和注意事项,比如对特定寄存器的写入可能会导致处理器复位或者影响其他功能。
君正X2000寄存器手册是开发者进行系统级编程和硬件驱动开发的重要参考资料,它详细列出了所有必要的寄存器信息,帮助开发者深入理解并充分利用X2000处理器的能力。对于任何使用这款处理器的项目来说,它是不可或缺的技术文档。
CONTENTS
xiv
X2000 IoT Application Processor Programming Manual
Copyright © 2005-2021 Ingenic Semiconductor Co., Ltd. All rights reserved.
22.2.3 Interrupt Controller Mask Register (ICMR0) ................................................................ 681
22.2.4 Interrupt Controller Mask Register (ICMR1) ................................................................ 682
22.2.5 Interrupt Controller Mask Set Register (ICMSR0) ....................................................... 682
22.2.6 Interrupt Controller Mask Set Register (ICMSR1) ....................................................... 682
22.2.7 Interrupt Controller Mask Clear Register (ICMCR0) .................................................... 683
22.2.8 Interrupt Controller Mask Clear Register (ICMCR1) .................................................... 683
22.2.9 Interrupt Controller Pending Register (ICPR0) ............................................................ 683
22.2.10 Interrupt Controller Pending Register (ICPR1) ........................................................ 684
22.2.11 Interrupt Source Register0 for PDMA (DSR0) ......................................................... 684
22.2.12 Interrupt Mask Register0 for PDMA (DMR0) ........................................................... 685
22.2.13 Interrupt Pending Register0 for PDMA (DPR0) ....................................................... 685
22.2.14 Interrupt Source Register1 to PDMA (DSR1) .......................................................... 685
22.2.15 Interrupt Mask Register1 for PDMA (DMR1) ........................................................... 686
22.2.16 Interrupt Pending Register1 for PDMA (DPR1) ....................................................... 686
22.3 Software Considerations ..................................................................................................... 687
23 Watchdog Timer ............................................................................. 688
23.1 Overview .............................................................................................................................. 688
23.2 Features .............................................................................................................................. 688
23.3 Register Description ............................................................................................................ 688
23.3.1 Register Memory Map ................................................................................................. 689
23.3.2 Register and Fields Description ................................................................................... 689
23.3.3 Watchdog Timer Data Register (WDT_FULL,0x00) .................................................... 689
23.3.4 Watchdog Enable Register (WDT_ENABLE,0x04) ..................................................... 689
23.3.5 Watchdog Timer Counter (WDT_COUNT,0x08) .......................................................... 690
23.3.6 Watchdog Control Register(WDT_CONTROL,0x0C) .................................................. 690
23.4 Watchdog Timer Function .................................................................................................... 691
24 PDMA Controller ............................................................................. 692
24.1 Overview .............................................................................................................................. 692
24.2 Features .............................................................................................................................. 692
24.3 Block Diagram ..................................................................................................................... 692
24.4 Memory Mapped Register Descriptions .............................................................................. 693
24.4.1 DMA Channel Registers .............................................................................................. 693
24.4.2 Global Control Registers .............................................................................................. 694
24.5 DMA Channel Register Definition ........................................................................................ 694
24.5.1 DMA Source Address (DSAn, n = 0 ~ 31) ................................................................... 694
24.5.2 DMA Target Address (DTAn, n = 0 ~ 31) ..................................................................... 695
24.5.3 DMA Transfer Count (DTCn, n = 0 ~ 31) ..................................................................... 695
24.5.4 DMA Request Types (DRTn, n = 0 ~ 31) ..................................................................... 695
24.5.5 DMA Channel Control/Status (DCSn, n = 0 ~ 31) ....................................................... 697
24.5.6 DMA Channel Command (DCMn, n = 0 ~ 31) ............................................................. 698
24.5.7 DMA Descriptor Address (DDAn, n = 0 ~ 31) .............................................................. 702
CONTENTS
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X2000 IoT Application Processor Programming Manual
Copyright © 2005-2021 Ingenic Semiconductor Co., Ltd. All rights reserved.
24.5.8 DMA Stride Difference (DSDn, n = 0 ~ 31) ................................................................. 703
24.6 DMA Global Register Definition .......................................................................................... 703
24.6.1 DMA Control ................................................................................................................ 703
24.6.2 DMA Interrupt Pending (DIRQP) ................................................................................. 704
24.6.3 DMA Doorbell (DDB) ................................................................................................... 705
24.6.4 DMA Doorbell Set (DDS) ............................................................................................. 705
24.6.5 Descriptor Interrupt Pending (DIP) .............................................................................. 705
24.6.6 Descriptor Interrupt Clear (DIC) .................................................................................. 706
24.6.7 DMA Channel Programmable (DMACP) ..................................................................... 706
24.6.8 DMA Soft IRQ Pending (DSIRQP) .............................................................................. 706
24.6.9 DMA Soft IRQ Mask (DSIRQM) .................................................................................. 707
24.6.10 DMA Channel IRQ Pending to MCU (DCIRQP) ...................................................... 707
24.6.11 DMA Channel IRQ to MCU Mask (DCIRQM) .......................................................... 708
24.6.12 Programmable Channel Bound With INTC_IRQ ..................................................... 708
24.6.13 Special Channel 0 and Channel 1 ........................................................................... 708
24.7 MCU .................................................................................................................................... 709
24.7.1 MCU Control & Status ................................................................................................. 709
24.7.2 MCU Normal MailBox .................................................................................................. 710
24.7.3 MCU Security MailBox ................................................................................................ 710
24.7.4 MCU Interrupt .............................................................................................................. 710
24.7.5 Multiple Bank Tightly Coupled Sharing Memory .......................................................... 711
24.7.6 CP0 Registers of MCU ................................................................................................. 711
24.7.7 Normal Exceptions Accepted by MCU ........................................................................ 712
24.7.8 How to Boot MCU Up .................................................................................................. 712
24.7.9 Security features ......................................................................................................... 713
24.8 DMA manipulation ............................................................................................................... 713
24.8.1 Descriptor Transfer Mode ............................................................................................ 713
24.8.2 No-Descriptor Transfer Mode ...................................................................................... 716
24.8.3 Descriptor Transfer Interrupt/Stop control ................................................................... 716
24.9 DMA Requests .................................................................................................................... 718
24.9.1 Auto Request ............................................................................................................... 718
24.9.2 On-Chip Peripheral Request ....................................................................................... 718
24.10 How to Use Programmable DMA Channel ......................................................................... 718
25 SAR A/D Controller ........................................................................ 719
25.1 Overview ............................................................................................................................. 719
25.2 Features .............................................................................................................................. 719
25.3 Block Diagram ..................................................................................................................... 719
25.4 Pins Description .................................................................................................................. 719
25.5 Register Description ............................................................................................................ 720
25.5.1 Register Memory Map ................................................................................................. 720
25.5.2 Register and Fields Description .................................................................................. 721
25.6 SAR A/D Controller Guide................................................................................................... 726
CONTENTS
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X2000 IoT Application Processor Programming Manual
Copyright © 2005-2021 Ingenic Semiconductor Co., Ltd. All rights reserved.
25.6.1 Power Down Mode ...................................................................................................... 726
25.6.2 AUX Sample Operation ............................................................................................... 727
26 Real Time Clock ............................................................................. 728
26.1 Overview .............................................................................................................................. 728
26.2 Features .............................................................................................................................. 728
26.3 Block Diagram ..................................................................................................................... 728
26.4 Pins Description................................................................................................................... 729
26.5 Registers Description .......................................................................................................... 729
26.5.1 RTC Control Register (RTCCR) .................................................................................. 731
26.5.2 RTC Second Register (RTCSR) .................................................................................. 732
26.5.3 RTC Second Alarm Register (RTCSAR) ..................................................................... 733
26.5.4 RTC Regulator Register (RTCGR) .............................................................................. 733
26.5.5 Hibernate Control Register (HCR) ............................................................................... 734
26.5.6 HIBERNATE mode Wakeup Filter Counter Register (HWFCR) .................................. 735
26.5.7 Hibernate Reset Counter Register (HRCR) ................................................................. 735
26.5.8 HIBERNATE Wakeup Control Register (HWCR) ......................................................... 736
26.5.9 HIBERNATE Wakeup Status Register (HWRSR) ........................................................ 736
26.5.10 Hibernate Scratch Pattern Register (HSPR) ............................................................ 737
26.5.11 Write Enable Pattern Register (WENR) ................................................................... 738
26.5.12 WKUP_PIN_RST control register (WKUPPINCR) ................................................... 739
26.6 Operation Flow .................................................................................................................... 739
26.6.1 Registers Access ......................................................................................................... 739
26.6.2 Registers Read ............................................................................................................ 739
26.6.3 Registers Write ............................................................................................................ 740
26.6.4 Normal Mode ............................................................................................................... 740
26.6.5 Power Detect ............................................................................................................... 740
26.6.6 Power On Timing Diagram ........................................................................................... 740
26.6.7 HIBERNATE Mode ....................................................................................................... 740
26.6.8 Procedure to Enter HIBERNATE mode ....................................................................... 741
26.6.9 Procedure to Wake-up from HIBERNATE mode ......................................................... 741
26.6.10 Time Regulation ....................................................................................................... 741
26.6.11 Clock select .............................................................................................................. 742
27 EFUSE Slave Interface (EFUSE) ................................................... 744
27.1 Overview .............................................................................................................................. 744
27.2 Registers ............................................................................................................................. 744
27.2.1 Registers Memory Map ................................................................................................ 745
27.2.2 Registers and Fields Description ................................................................................. 745
27.3 Operation Mode ................................................................................................................... 750
27.4 Flow ..................................................................................................................................... 751
27.4.1 Program EFUSE Flow ................................................................................................. 751
27.4.2 Program Security Key Flow ......................................................................................... 751
CONTENTS
xvii
X2000 IoT Application Processor Programming Manual
Copyright © 2005-2021 Ingenic Semiconductor Co., Ltd. All rights reserved.
27.4.3 Read EFUSE Flow ...................................................................................................... 752
27.4.4 Read Security Key Flow .............................................................................................. 752
PERIPHERALS ................................................................................... 753
28 General-Purpose I/O Ports ............................................................ 754
28.1 Overview ............................................................................................................................. 754
28.2 Features .............................................................................................................................. 754
28.3 About GPIO Port Summary Table ....................................................................................... 754
28.3.1 GPIO Port A Summary ................................................................................................ 757
28.3.2 GPIO Port B Summary ................................................................................................ 758
28.3.3 GPIO Port C Summary ................................................................................................ 759
28.3.4 GPIO Port D Summary ................................................................................................ 760
28.3.5 GPIO Port E Summary ................................................................................................ 761
28.3.6 GPIO Port Z - Shadow Group ..................................................................................... 763
28.4 Registers Description .......................................................................................................... 763
28.4.1 Register Memory Map ................................................................................................. 763
28.4.2 Register and Fields Description .................................................................................. 769
28.4.3 PORT PIN Level Registers (PxPINL,0x0000) ............................................................. 769
28.4.4 PORT Interrupt Registers (PxINT,0x0010) .................................................................. 770
28.4.5 PORT Interrupt Set Registers (PxINTS,0x0014) ......................................................... 770
28.4.6 PORT Interrupt Clear Registers (PxINTC,0x0018) ..................................................... 770
28.4.7 PORT Mask Registers (PxMSK,0x0020) .................................................................... 771
28.4.8 PORT Mask Set Registers (PxMSKS,0x0024) ........................................................... 771
28.4.9 PORT Mask Clear Registers (PxMSKC,0x0028) ........................................................ 772
28.4.10 PORT PAT1/Direction Registers (PxPAT1,0x0030) ................................................. 772
28.4.11 PORT PAT1/Direction Set Registers (PxPAT1S,0x0034) ........................................ 773
28.4.12 PORT PAT1/Direction Clear Registers (PxPAT1C,0x0038) .................................... 773
28.4.13 PORT PAT0/Data Registers (PxPAT0,0x0040) ....................................................... 774
28.4.14 PORT PAT0/Data Set Registers (PxPAT0S,0x0044) .............................................. 774
28.4.15 PORT PAT0/Data Clear Registers (PxPAT0C,0x0048) ........................................... 775
28.4.16 PORT FLAG Registers (PxFLG,0x0050) ................................................................ 775
28.4.17 PORT FLAG Clear Registers (PxFLGC,0x0058) .................................................... 776
28.4.18 PORT Dual-Edge Interrupt Register (PxEDG,0x70) ............................................... 776
28.4.19 PORT Dual-Edge Interrupt Set Register (PxEDGS,0x74)....................................... 777
28.4.20 PORT Dual-Edge Interrupt Clear Register (PxEDGC,0x78) ................................... 777
28.4.21 PORT PULL-UP State Register (PxPU,0x80) ......................................................... 777
28.4.22 PORT PULL-UP State Set Register (PxPUS,0x84) ................................................ 779
28.4.23 PORT PULL-UP State Clear Register (PxPUC,0x88) ............................................. 780
28.4.24 PORT PULL-DOWN State Register (PxPD,0x90) ................................................... 780
28.4.25 PORT PULL-DOWN State Set Register (PxPDS,0x94) .......................................... 782
28.4.26 PORT PULL-DOWN State Clear Register (PxPDC,0x98) ...................................... 782
28.4.27 PORT Drive Strength State Register0 (PxDS0,0xA0) ............................................. 782
CONTENTS
xviii
X2000 IoT Application Processor Programming Manual
Copyright © 2005-2021 Ingenic Semiconductor Co., Ltd. All rights reserved.
28.4.28 PORT Drive Strength State Set Register0 (PxDS0S,0xA4) .................................... 783
28.4.29 PORT Drive Strength State Clear Register0 (PxDS0C,0xA8) ................................. 783
28.4.30 PORT Drive Strength State Register1 (PxDS1,0xB0) ............................................. 784
28.4.31 PORT Drive Strength State Set Register1 (PxDS1S,0xB4) .................................... 784
28.4.32 PORT Drive Strength State Clear Register1 (PxDS1C,0xB8) ................................. 784
28.4.33 PORT Drive Strength State Register2 (PxDS2,0xC0) ............................................. 785
28.4.34 PORT Drive Strength State Set Register2 (PxDS2S,0xC4) .................................... 785
28.4.35 PORT Drive Strength State Clear Register2 (PxDS2C,0xC8) ................................. 786
28.4.36 PORT Slew Rate Register (PxSR,0xD0) ................................................................. 786
28.4.37 PORT Slew Rate Set Register (PxSRS,0xD4) ........................................................ 786
28.4.38 PORT Slew Rate Clear Register (PxSRC,0xD8) ..................................................... 787
28.4.39 PORT Schmitt Trigger Register (PxSMT,0xE0) ....................................................... 787
28.4.40 PORT Schmitt Trigger Set Register (PxSMTS,0xE4) .............................................. 787
28.4.41 PORT Schmitt Trigger Clear Register (PxSMTC,0xE8) ........................................... 788
28.4.42 PORT Z Shadow Register Group ............................................................................ 788
28.4.43 GPIOZ Group ID to Load Register (PzGID2LD,0x00F0) ......................................... 790
28.5 Program Guide .................................................................................................................... 791
28.5.1 Port Function Guide ..................................................................................................... 791
28.5.2 Configure without 3rd-unexpected state ...................................................................... 791
28.5.3 Dual-edge Interrupt Configure Guide .......................................................................... 792
29 SMB Controller ............................................................................... 793
29.1 Overview .............................................................................................................................. 793
29.1.1 Features ....................................................................................................................... 793
29.1.2 Pin Description ............................................................................................................. 793
29.2 Registers ............................................................................................................................. 794
29.2.1 Registers Memory Map ................................................................................................ 794
29.2.2 Registers and Fields Description ................................................................................. 795
29.2.3 SMB_CON (SMB Control Register) ............................................................................. 795
29.2.4 SMB_TAR (SMB Target Address Register) ................................................................. 796
29.2.5 SMB_SAR (SMB Slave Address Register) .................................................................. 798
29.2.6 SMB_HS_MADDR (SMB High Speed Master Mode Code Address Register) ........... 798
29.2.7 SMB_DC (SMB Rx/Tx Data Buffer and Command Register) ...................................... 799
29.2.8 SMB_SHCNT (SMB Standard Speed SCL High Count Register) ............................... 800
29.2.9 SMB_SLCNT (SMB Standard Speed SCL Low Count Register) ................................ 801
29.2.10 SMB_FHCNT (SMB Fast Speed SCL High Count Register) ................................... 801
29.2.11 SMB_FLCNT (SMB Fast Speed SCL Low Count Register) .................................... 802
29.2.12 SMB_HHCNT (SMB High Speed SCL High Count Register) .................................. 802
29.2.13 SMB_HLCNT (SMB High Speed SCL Low Count Register) ................................... 803
29.2.14 SMB_INTST (SMB Interrupt Status Register) ......................................................... 803
29.2.15 SMB_INTM (SMB Interrupt Mask Register) ............................................................. 805
29.2.16 SMB_RAW_INTR_STAT .......................................................................................... 806
29.2.17 SMB_RXTL (SMB Receive FIFO Threshold Register) ............................................ 808
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