"STM32H7x3和STM32H750单片机参考手册1：详尽信息及应用指南"

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The "RM0433_STM32H7x3 and STM32H750 Single-Chip Microcontroller Reference Manual" is a comprehensive guide for application developers, released in February 2020. It covers the STM32H742, STM32H743/753, and STM32H750 Value Line microcontrollers, providing detailed information on memory usage, peripherals, and package options. These advanced Arm®-based 32-bit MCUs offer a range of memory sizes and peripherals to suit various application requirements. The reference manual is organized to provide developers with complete information on utilizing the capabilities of the STM32H742xx, STM32H743/53xx, and STM32H750xB microcontrollers. It includes detailed descriptions of memory organization, peripheral interfaces, and system configuration options. This allows developers to efficiently design and implement their applications using these microcontrollers. Additionally, the manual provides ordering information, mechanical specifications, and other details necessary for procuring and integrating the STM32H742, STM32H743/753, and STM32H750 microcontrollers into a specific application. It serves as a valuable resource for developers looking to leverage the advanced features and performance of these microcontrollers in their designs. In conclusion, the "RM0433_STM32H7x3 and STM32H750 Single-Chip Microcontroller Reference Manual" is an essential tool for application developers seeking to maximize the potential of the STM32H742, STM32H743/753, and STM32H750 microcontrollers. With its comprehensive coverage of memory, peripherals, and system configuration, it provides the necessary information to enable efficient and effective utilization of these advanced microcontrollers in various applications. This reference manual serves as a valuable resource for both experienced and novice developers, showcasing the capabilities and features of the STM32H7x3 and STM32H750 microcontrollers.

Contents RM0433

16/3319 RM0433 Rev 7

15.5.4 DMA high interrupt flag clear register (DMA_HIFCR) . . . . . . . . . . . . . 658

15.5.5 DMA stream x configuration register (DMA_SxCR) . . . . . . . . . . . . . . . 659

15.5.6 DMA stream x number of data register (DMA_SxNDTR) . . . . . . . . . . 662

15.5.7 DMA stream x peripheral address register (DMA_SxPAR) . . . . . . . . . 663

15.5.8 DMA stream x memory 0 address register

(DMA_SxM0AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

15.5.9 DMA stream x memory 1 address register

(DMA_SxM1AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

15.5.10 DMA stream x FIFO control register (DMA_SxFCR) . . . . . . . . . . . . . . 664

15.5.11 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

16 Basic direct memory access controller (BDMA) . . . . . . . . . . . . . . . . 670

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

16.2 BDMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

16.3 BDMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

16.3.1 BDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

16.3.2 BDMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

16.4 BDMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

16.4.1 BDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

16.4.2 BDMA pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

16.4.3 BDMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

16.4.4 BDMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

16.4.5 BDMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

16.4.6 BDMA data width, alignment and endianness . . . . . . . . . . . . . . . . . . . 678

16.4.7 BDMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679

16.5 BDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

16.6 BDMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

16.6.1 BDMA interrupt status register (BDMA_ISR) . . . . . . . . . . . . . . . . . . . . 680

16.6.2 BDMA interrupt flag clear register (BDMA_IFCR) . . . . . . . . . . . . . . . . 683

16.6.3 BDMA channel x configuration register (BDMA_CCRx) . . . . . . . . . . . 684

16.6.4 BDMA channel x number of data to transfer register

(BDMA_CNDTRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688

16.6.5 BDMA channel x peripheral address register (BDMA_CPARx) . . . . . . 688

16.6.6 BDMA channel x memory 0 address register (BDMA_CM0ARx) . . . . 689

16.6.7 BDMA channel x memory 1 address register (BDMA_CM1ARx) . . . . 690

16.6.8 BDMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

RM0433 Rev 7 17/3319

RM0433 Contents

17 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . 693

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

17.2 DMAMUX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

17.3 DMAMUX implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

17.3.1 DMAMUX1 and DMAMUX2 instantiation . . . . . . . . . . . . . . . . . . . . . . . 694

17.3.2 DMAMUX1 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

17.3.3 DMAMUX2 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

17.4 DMAMUX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

17.4.1 DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

17.4.2 DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

17.4.3 DMAMUX channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

17.4.4 DMAMUX request line multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

17.4.5 DMAMUX request generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

17.5 DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

17.6 DMAMUX registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

17.6.1 DMAMUX1 request line multiplexer channel x configuration register

(DMAMUX1_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

17.6.2 DMAMUX2 request line multiplexer channel x configuration register

(DMAMUX2_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

17.6.3 DMAMUX1 request line multiplexer interrupt channel status register

(DMAMUX1_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707

17.6.4 DMAMUX2 request line multiplexer interrupt channel status register

(DMAMUX2_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707

17.6.5 DMAMUX1 request line multiplexer interrupt clear flag register

(DMAMUX1_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

17.6.6 DMAMUX2 request line multiplexer interrupt clear flag register

(DMAMUX2_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

17.6.7 DMAMUX1 request generator channel x configuration register

(DMAMUX1_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

17.6.8 DMAMUX2 request generator channel x configuration register

(DMAMUX2_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

17.6.9 DMAMUX1 request generator interrupt status register

(DMAMUX1_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710

17.6.10 DMAMUX2 request generator interrupt status register

(DMAMUX2_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

17.6.11 DMAMUX1 request generator interrupt clear flag register

(DMAMUX1_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

17.6.12 DMAMUX2 request generator interrupt clear flag register

(DMAMUX2_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

17.6.13 DMAMUX register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

Contents RM0433

18/3319 RM0433 Rev 7

18 Chrom-Art Accelerator™ controller (DMA2D) . . . . . . . . . . . . . . . . . . 715

18.1 DMA2D introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715

18.2 DMA2D main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715

18.3 DMA2D functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716

18.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716

18.4 DMA2D pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

18.4.1 DMA2D control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

18.4.2 DMA2D foreground and background FIFOs . . . . . . . . . . . . . . . . . . . . 718

18.4.3 DMA2D foreground and background pixel format converter (PFC) . . . 718

18.4.4 DMA2D foreground and background CLUT interface . . . . . . . . . . . . . 721

18.4.5 DMA2D blender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

18.4.6 DMA2D output PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

18.4.7 DMA2D output FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

18.4.8 DMA2D output FIFO byte reordering . . . . . . . . . . . . . . . . . . . . . . . . . . 723

18.4.9 DMA2D AXI master port timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

18.4.10 DMA2D transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

18.4.11 DMA2D configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

18.4.12 YCbCr support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730

18.4.13 DMA2D transfer control (start, suspend, abort and completion) . . . . . 730

18.4.14 Watermark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730

18.4.15 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

18.4.16 AXI dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

18.5 DMA2D interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

18.6 DMA2D registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

18.6.1 DMA2D control register (DMA2D_CR) . . . . . . . . . . . . . . . . . . . . . . . . 732

18.6.2 DMA2D interrupt status register (DMA2D_ISR) . . . . . . . . . . . . . . . . . 734

18.6.3 DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . . . . . . . . . . . 735

18.6.4 DMA2D foreground memory address register (DMA2D_FGMAR) . . . 736

18.6.5 DMA2D foreground offset register (DMA2D_FGOR) . . . . . . . . . . . . . . 736

18.6.6 DMA2D background memory address register (DMA2D_BGMAR) . . 737

18.6.7 DMA2D background offset register (DMA2D_BGOR) . . . . . . . . . . . . . 737

18.6.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . . 738

18.6.9 DMA2D foreground color register (DMA2D_FGCOLR) . . . . . . . . . . . . 740

18.6.10 DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . 741

18.6.11 DMA2D background color register (DMA2D_BGCOLR) . . . . . . . . . . . 743

RM0433 Rev 7 19/3319

RM0433 Contents

18.6.12 DMA2D foreground CLUT memory address register

(DMA2D_FGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743

18.6.13 DMA2D background CLUT memory address register

(DMA2D_BGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744

18.6.14 DMA2D output PFC control register (DMA2D_OPFCCR) . . . . . . . . . . 744

18.6.15 DMA2D output color register (DMA2D_OCOLR) . . . . . . . . . . . . . . . . . 745

18.6.16 DMA2D output memory address register (DMA2D_OMAR) . . . . . . . . 747

18.6.17 DMA2D output offset register (DMA2D_OOR) . . . . . . . . . . . . . . . . . . 747

18.6.18 DMA2D number of line register (DMA2D_NLR) . . . . . . . . . . . . . . . . . 748

18.6.19 DMA2D line watermark register (DMA2D_LWR) . . . . . . . . . . . . . . . . . 748

18.6.20 DMA2D AXI master timer configuration register (DMA2D_AMTCR) . . 749

18.6.21 DMA2D foreground CLUT (DMA2D_FGCLUT[y]) . . . . . . . . . . . . . . . . 749

18.6.22 DMA2D background CLUT (DMA2D_BGCLUT[y]) . . . . . . . . . . . . . . . 750

18.6.23 DMA2D register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

19 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 753

19.1 NVIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

19.1.1 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

19.1.2 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754

20 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . 762

20.1 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

20.2 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

20.2.1 EXTI connections between peripherals, CPU, and D3 domain . . . . . . 763

20.3 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764

20.3.1 EXTI Configurable event input CPU wakeup . . . . . . . . . . . . . . . . . . . . 765

20.3.2 EXTI configurable event input Any wakeup . . . . . . . . . . . . . . . . . . . . . 766

20.3.3 EXTI direct event input CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . 768

20.3.4 EXTI direct event input Any wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . 769

20.3.5 EXTI D3 pending request clear selection . . . . . . . . . . . . . . . . . . . . . . 770

20.4 EXTI event input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

20.5 EXTI functional behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773

20.5.1 EXTI CPU interrupt procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

20.5.2 EXTI CPU event procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

20.5.3 EXTI CPU wakeup procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775

20.5.4 EXTI D3 domain wakeup for autonomous Run mode procedure . . . . 775

20.5.5 EXTI software interrupt/event trigger procedure . . . . . . . . . . . . . . . . . 775

Contents RM0433

20/3319 RM0433 Rev 7

20.6 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

20.6.1 EXTI rising trigger selection register (EXTI_RTSR1) . . . . . . . . . . . . . . 776

20.6.2 EXTI falling trigger selection register (EXTI_FTSR1) . . . . . . . . . . . . . 776

20.6.3 EXTI software interrupt event register (EXTI_SWIER1) . . . . . . . . . . . 777

20.6.4 EXTI D3 pending mask register (EXTI_D3PMR1) . . . . . . . . . . . . . . . . 777

20.6.5 EXTI D3 pending clear selection register low (EXTI_D3PCR1L) . . . . 778

20.6.6 EXTI D3 pending clear selection register high (EXTI_D3PCR1H) . . . 778

20.6.7 EXTI rising trigger selection register (EXTI_RTSR2) . . . . . . . . . . . . . . 779

20.6.8 EXTI falling trigger selection register (EXTI_FTSR2) . . . . . . . . . . . . . 780

20.6.9 EXTI software interrupt event register (EXTI_SWIER2) . . . . . . . . . . . 780

20.6.10 EXTI D3 pending mask register (EXTI_D3PMR2) . . . . . . . . . . . . . . . . 781

20.6.11 EXTI D3 pending clear selection register low (EXTI_D3PCR2L) . . . . 782

20.6.12 EXTI D3 pending clear selection register high (EXTI_D3PCR2H) . . . 782

20.6.13 EXTI rising trigger selection register (EXTI_RTSR3) . . . . . . . . . . . . . . 783

20.6.14 EXTI falling trigger selection register (EXTI_FTSR3) . . . . . . . . . . . . . 783

20.6.15 EXTI software interrupt event register (EXTI_SWIER3) . . . . . . . . . . . 784

20.6.16 EXTI D3 pending mask register (EXTI_D3PMR3) . . . . . . . . . . . . . . . . 784

20.6.17 EXTI D3 pending clear selection register low (EXTI_D3PCR3L) . . . . 785

20.6.18 EXTI D3 pending clear selection register high (EXTI_D3PCR3H) . . . 785

20.6.19 EXTI interrupt mask register (EXTI_CPUIMR1) . . . . . . . . . . . . . . . . . 786

20.6.20 EXTI event mask register (EXTI_CPUEMR1) . . . . . . . . . . . . . . . . . . . 786

20.6.21 EXTI pending register (EXTI_CPUPR1) . . . . . . . . . . . . . . . . . . . . . . . 787

20.6.22 EXTI interrupt mask register (EXTI_CPUIMR2) . . . . . . . . . . . . . . . . . 787

20.6.23 EXTI event mask register (EXTI_CPUEMR2) . . . . . . . . . . . . . . . . . . . 788

20.6.24 EXTI pending register (EXTI_CPUPR2) . . . . . . . . . . . . . . . . . . . . . . . 788

20.6.25 EXTI interrupt mask register (EXTI_CPUIMR3) . . . . . . . . . . . . . . . . . 789

20.6.26 EXTI event mask register (EXTI_CPUEMR3) . . . . . . . . . . . . . . . . . . . 790

20.6.27 EXTI pending register (EXTI_CPUPR3) . . . . . . . . . . . . . . . . . . . . . . . 790

20.6.28 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791

21 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 794

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794

21.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794

21.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795

21.3.1 CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795

21.3.2 CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795

21.3.3 CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795

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