TVP5150视频解码器：超低功耗NTSC/PAL/SECAM解码方案

3星 · 超过75%的资源需积分: 10 124 浏览量更新于2024-07-29 收藏 926KB PDF 举报

TVP5150是一款专为视频解码设计的高性能芯片，它在IT行业中被广泛应用于低功耗NTSC、PAL和SECAM标准的视频信号处理。这款视频Decode IC以其超低功耗特性而受到青睐，其紧凑的封装形式（如TVP5150AM1U）使得它在小型设备和嵌入式系统中具有高度的集成度和灵活性。 TVP5150A/TVP5150AM1的核心功能包括但不限于：视频信号解码，能够处理模拟电视信号并将其转换为数字信号，以便于后续的处理、存储或传输。它支持多种视频标准，确保了广泛的兼容性，这对于多媒体设备和系统来说是至关重要的，因为它们可能需要适应不同地区或地区的电视广播标准。文献编号SLES098A提供了关于该产品的详细规格和使用指南，发布日期为2005年4月，后续在2006年3月进行了修订。值得注意的是，德州仪器（Texas Instruments, TI）作为制造商，保留随时对产品性能、设计、服务进行改进的权利，并有权在未提前通知的情况下停止供应某些产品或服务。因此，在下单前，用户应确保获取最新的相关信息，并确认其准确性和完整性。 TI的保修政策保障了硬件产品的性能符合销售时适用的标准，但并不保证对所有参数进行全面测试。此外，TI不对应用支持或客户产品设计承担法律责任，除非政府要求。这意味着用户在使用TVP5150时，需要自行评估和设计其应用场景，确保正确使用。 TVP5150是一款适用于低功耗场景的高效视频解码器，它在现代多媒体设备中的应用广泛，但用户在采用时需注意其可能的更新和限制，确保遵循制造商的指导和最佳实践。对于系统设计师和开发人员来说，了解这款芯片的功能特性和TI的政策是至关重要的，以实现高质量的产品和良好的用户体验。

Introduction

April 2005 − Revised March 2006 SLES098A

2.9 Terminal Assignments

The TVP5150A video decoder bridge is packaged in a 32-terminal PBS package or a 48-terminal ZQC

package. Figure 2−2 is the PBS-package and ZQC-package terminal diagrams. Table 2−1 gives a description

of the terminals.

TQFP PACKAGE

(TOP VIEW)

31 30 29 28 27

PCLK/SCLK

IO_DVDD

YOUT7/I2CSEL

YOUT6

YOUT5

YOUT4

YOUT3

YOUT2

CH_AVDD

CH_AGND

REFM

REFP

PDN

INTREQ/GPCL/VBLK

AVID

HSYNC

32 26 25

VSYNC/PALI

FID/GLCO

SDA

SCL

DVDD

DGND

YOUT0

YOUT1

AIP1A

AIP1B

PLL_AGND

PLL_AVDD

XTAL1/OSC

XTAL2

AGND

RESETB

10 11 12 13 1491516

234 56

ZQC PACKAGE

(BOTTOM VIEW)

Figure 2−2. TVP5150A PBS-Package Terminal Diagrams

Introduction

April 2005 − Revised March 2006SLES098A

Table 2−1. Terminal Functions

TERMINAL

NAME

NUMBER

I/O DESCRIPTION

NAME

PBS ZQC

I/O

DESCRIPTION

Analog Section

AGND 7 E1 I Substrate. Connect to analog ground.

AIP1A 1 A1 I

Analog input: composite or S-video (luma). Connect to the video analog input via 0.1-µF

capacitor. The maximum input range is 0−0.75 V

, and may require an attenuator to reduce

the input amplitude to the desired level. If not used, connect to AGND via 0.1-µF capacitor. Refer

to Figure 6−1.

AIP1B 2 B1 I

Analog input: composite or S-video (chroma). Connect to the video analog input via 0.1-µF

capacitor. The maximum input range is 0−0.75 V

, and may require an attenuator to reduce

the input amplitude to the desired level. If not used, connect to AGND via 0.1-µF capacitor. Refer

to Figure 6−1.

CH_AGND 31 A3 I Analog ground

CH_AVDD 32 A2 I Analog supply. Connect to 1.8-V analog supply.

NC −

B2, B3, B6, C4,

C5, D3−D6,

E2−E5, F2, F5,

− No connect

PLL_AGND 3 C2 I PLL ground. Connect to analog ground.

PLL_AVDD 4 C1 I PLL supply. Connect to 1.8-V analog supply.

REFM 30 A4 I

A/D reference ground. Connect to analog ground through 1-µF capacitor. Also, it is

recommended to connect directly to REFP through 1-µF capacitor. Refer to Figure 6−1.

REFP 29 B4 I A/D reference supply. Connect to analog ground through 1-µF capacitor. Refer to Figure 6−1.

Digital Section

AVID 26 A6 O

Active video indicator. This signal is high during the horizontal active time of the video output.

AVID toggling during vertical blanking intervals is controlled by bit 2 of the active video cropping

start pixel LSB register at address 12h (see Section 3.20.17).

DGND 19 E6 I Digital ground

DVDD 20 E7 I Digital supply. Connect to 1.8-V digital supply

FID/GLCO 23 C6 O

FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates

the odd field.

GLCO: This serial output carries color PLL information. A slave device can decode the

information to allow chroma frequency control from the TVP5150A decoder. Data is transmitted

at the SCLK rate in Genlock mode. In RTC mode, SCLK/4 is used.

HSYNC 25 A7 O Horizontal synchronization signal

INTREQ/

GPCL/

VBLK

27 B5 I/O

INTREQ: Interrupt request output.

GPCL/VBLK: General-purpose control logic. This terminal has two functions:

1. GPCL: General-purpose output. In this mode the state of GPCL is directly programmed via

2. VBLK: Vertical blank output. In this mode the GPCL terminal indicates the vertical blanking

interval of the output video. The beginning and end times of this signal are programmable via

IO_DVDD 10 G2 I Digital supply. Connect to 3.3 V.

PCLK/

SCLK

9 G1 O System clock at either 1x or 2x the frequency of the pixel clock.

PDN 28 A5 I

Power-down terminal (active low). Puts the decoder in standby mode. Preserves the value of

the registers.

RESETB 8 F1 I

Active-low reset. RESETB can be used only when PDN = 1.

When RESETB is pulled low, it resets all the registers and restarts the internal microprocessor.

SCL 21 D7 I/O I

C serial clock (open drain)

SDA 22 C7 I/O I

C serial data (open drain)

Functional Description

April 2005 − Revised March 2006SLES098A

3 Functional Description

3.1 Analog Front End

The TVP5150A decoder has an analog input channel that accepts two video inputs, which are ac-coupled.

The decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is

needed for most input signals with a peak-to-peak variation of 1.5 V. The maximum parallel termination before

the input to the device is 75 Ω. Please refer to the applications diagram in Figure 6−1 for the recommended

configuration. The two analog input ports can be connected as follows:

• Two selectable composite video inputs or

• One S-video input

An internal clamping circuit restores the ac-coupled video signal to a fixed dc level.

The programmable gain amplifier (PGA) and the AGC circuit work together to make sure that the input signal

is amplified sufficiently to ensure the proper input range for the ADC.

The ADC has 9 bits of resolution and runs at a maximum speed of 27 MHz. The clock input for the ADC comes

from the PLL.

3.2 Composite Processing Block Diagram

The composite processing block processes NTSC/PAL/SECAM signals into the YCbCr color space.

Figure 3−1 explains the basic architecture of this processing block.

Figure 3−1 illustrates the luminance/chrominance (Y/C) separation process in the TVP5150A decoder. The

composite video is multiplied by subcarrier signals in the quadrature modulator to generate the color difference

signals Cb and Cr. Cb and Cr are then low-pass (LP) filtered to achieve the desired bandwidth and to reduce

crosstalk.

An adaptive 4-line comb filter separates CbCr from Y. Chroma is remodulated through another quadrature

modulator and subtracted from the line-delayed composite video to generate luma. Contrast, brightness, hue,

saturation, and sharpness (using the peaking filter) are programmable via I

The Y/C separation is bypassed for S-video input. For S-video, the remodulation path is disabled.

3.3 Adaptive Comb Filtering

The 4-line comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed

in the luma path, then chroma notch filters are used. TI’s patented adaptive 4-line comb filter algorithm reduces

artifacts such as hanging dots at color boundaries and detects and properly handles false colors in high

frequency luminance images such as a multiburst pattern or circle pattern.

3.4 Color Low-Pass Filter

In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true in

case of video signals that have asymmetrical Cb/Cr sidebands. The color LP filters provided limit the

bandwidth of the Cb/Cr signals.

Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input image.

Please refer to Section 3.20.25, Chrominance Control #2 Register, for the response of these filters. The filters

have three options that allow three different frequency responses based on the color frequency characteristics

of the input video.

剩余78页未读，继续阅读

star78

粉丝: 16

TVP5150视频解码器：超低功耗NTSC/PAL/SECAM解码方案

BT.656并行接口除了传输4:2:2的YCbCr视频数据流外

BT 656 Encoder 编码器模块（verilog）

DECODE解码代码

关于TVP5150AM1视频采集模块设计

如何通过I2C接口配置TVP5150芯片的I2CSEL引脚以及对应的寄存器，以选择不同的视频输入源？

如何通过I2C接口使用TVP5150芯片的I2CSEL引脚来设置不同的视频输入源？请提供详细的操作步骤。

tvp5150 verilog

tvp5150 程序

如何在嵌入式系统中使用TVP5146进行视频解码并处理模拟视频信号？

在嵌入式系统中如何利用TVP5146实现视频信号的采集与解码？

最新资源

tvp5150　verilog