IT8512E/F嵌入式控制器0.4.1初步规格概述：集成移动系统应用功能

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IT8512E/F嵌入式控制器预览规格说明书0.4.1提供了对一款高度集成的嵌入式控制器的详细介绍，这款控制器专为移动系统应用设计。该控制器的核心功能包括： 1. **LPC总线接口**：IT8512直接与系统连接到LPC（Low Pin Count）总线，这是主板上常见的接口，用于高效的数据传输和控制信号交互。 2. **ACPI嵌入式控制器功能**：作为系统控制器，它支持高级配置和电源接口（Advanced Configuration and Power Interface），这是一种现代计算机平台的标准，用于管理硬件和软件资源的电源状态。 3. **键盘控制器(KBC)与矩阵扫描**：提供键盘输入处理能力，通过矩阵扫描技术可以检测和解析键盘按键，确保精确的输入响应。 4. **外部闪存接口**：用于存储系统BIOS和EC（嵌入式控制）代码，这有助于简化固件管理，提高了系统的可升级性和可靠性。 5. **PWM（脉宽调制）与ADC（模拟到数字转换器）**：用于硬件监控，如风扇控制，实现智能自动风扇速度调整，以保持系统温度稳定。 6. **PS/2接口**：支持外部键盘和鼠标设备的连接，确保外部设备的兼容性。 7. **BRAM（静态随机存取内存）和CIR（唤醒控制器）**：这些内存用于存储临时数据和控制信号，支持系统电源管理，如睡眠和唤醒功能。 8. **外部闪存共享**：允许主机和EC（嵌入式控制器）共享外部存储，增强了数据共享和保护。值得注意的是，这份文档是初步规格，可能随时更新，因此在购买或使用前应联系销售代表获取最新信息。所有销售都遵循ITE公司的标准条款和条件，详细信息可在文档后部找到。此外，IT8512E/F是ITE Technology Inc.的注册商标，而文档中提及的所有其他商标属于其各自所有者。欲获取更多关于IT8512E/F嵌入式控制器的手册或其他ITE文献，请联系市场营销部门或赵阳（P.Y. Chang）先生，邮箱为p.y.chang@ite。IT8512E/F是一款多功能且高度集成的嵌入式控制器，适用于追求高效能、低功耗和可扩展性的笔记本主板设计。

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Contents

Figure 6-8. KBC Host Interface Block Diagram.................................................................................................96

Figure 6-9. IRQ Control in KBC Module............................................................................................................97

Figure 6-10. PMC Host Interface Block Diagram............................................................................................103

Figure 6-11. EC Interrupt Request for PMC....................................................................................................104

Figure 6-12. IRQ/SCI#/SMI# Control in PMC Compatible Mode....................................................................105

Figure 6-13. IRQ/SCI#/SMI# Control in PMC Enhanced Mode......................................................................106

Figure 6-14. Typical PMC2EX Mailbox Operation..........................................................................................107

Figure 7-1. Interrupt Control System Configuration........................................................................................127

Figure 7-2. Interrupt Response Time..............................................................................................................129

Figure 7-3. Timer 0/1 in Mode 0 and Mode 1..................................................................................................129

Figure 7-4. Timer 0/1 in Mode 2, Auto-Reload................................................................................................130

Figure 7-5. Timer 0 in Mode 3 Two 8-bit Timers.............................................................................................130

Figure 7-6. Timer 2: Capture Mode.................................................................................................................131

Figure 7-7. Timer 2: Auto Reload (DECN = 0)................................................................................................132

Figure 7-8. Timer 2: Auto Reload Mode (DECN = 1)......................................................................................133

Figure 7-9. Timer 2: Clock Out Mode..............................................................................................................134

Figure 7-10. Watchdog Timer..........................................................................................................................134

Figure 7-11. Serial Port Block Diagram...........................................................................................................135

Figure 7-12. Data Frame (Mode 1, 2 and 3)...................................................................................................136

Figure 7-13. Timer 2 in Baud Rate Generator Mode......................................................................................137

Figure 7-14. INTC Simplified Digram..............................................................................................................163

Figure 7-15. Program Flow Chart for INTC.....................................................................................................164

Figure 7-16. WUC Simplified Digram..............................................................................................................170

Figure 7-17. Program Flow Chart for WUC.....................................................................................................170

Figure 7-18. GPIO Simplified Diagram............................................................................................................181

Figure 7-19. ADC Channels Control Diagram.................................................................................................206

Figure 7-20. ADC Software Calibration Flow..................................................................................................219

Figure 7-21. ADC Software Calibration Flow in a Special Case.....................................................................220

Figure 7-22. PWM & SmartAuto Fan Block.....................................................................................................221

Figure 7-23. PWM Clock Tree.........................................................................................................................222

Figure 7-24. CR256 PWM Block Diagram......................................................................................................223

Figure 7-25. CR256 Base Pulse vs. Additional Pulse.....................................................................................225

Figure 7-26. SmartAuto Mode 1 Fan PWM output vs. Temperature Reading................................................227

Figure 7-27. Program Flow Chart for PWM Channel Output..........................................................................244

Figure 7-28. Program Flow Chart for SmartAuto Fan Channel Output...........................................................245

Figure 7-29. Program Flow Chart for EC2I Read............................................................................................249

Figure 7-30. Program Flow Chart for EC2I Write............................................................................................250

Figure 7-31. Simplified Diagram......................................................................................................................251

Figure 7-32. BRAM Mapping Diagram............................................................................................................264

Figure 7-33. Simplified Diagram......................................................................................................................266

Figure 7-34. Parallel Port Female 25-Pin Connector......................................................................................286

Figure 10-1. VSTBY Power-on Reset Timing.................................................................................................299

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Figure 10-2. Reset Timing...............................................................................................................................299

Figure 10-3. Warm Reset Timing....................................................................................................................300

Figure 10-4. Wakeup from Doze Mode Timing...............................................................................................300

Figure 10-5. Wake Up from Sleep Mode Timing.............................................................................................301

Figure 10-6. Asynchronous External Wakeup/Interrupt Source Edge Detected Timing.................................301

Figure 10-7. LPC and SERIRQ Timing...........................................................................................................301

Figure 10-8. SWUC Wake Up Timing............................................................................................................302

Figure 10-9. LPC/FWH Flash Cycle Timing....................................................................................................302

Figure 10-10. Serial Flash Cycle Timing.........................................................................................................303

Figure 10-11. PWM Output Timing................................................................................................................303

Figure 10-12. PMC SMI#/SCI# Timing...........................................................................................................304

Figure 10-13. PMC IBF/SCI# Timing.............................................................................................................304

Figure 10-14. PS/2 Receive/Transmit Timing................................................................................................305

Figure 10-15. SMBUS Timing........................................................................................................................306

Figure 10-16. Consumer IR (CIR) Timing.......................................................................................................307

Figure 10-17. External GPIO Controller Data Timing....................................................................................308

TABLES

Table 3-1. Host/Flash Mapping...........................................................................................................................7

Table 3-2. EC/Flash Mapping.............................................................................................................................8

Table 3-3. Flash Read/Write Protection Controlled by EC Side.........................................................................8

Table 3-4. Trusted ROM Range..........................................................................................................................8

Table 4-1. Pins Listed in Numeric Order (128-pin LQFP).................................................................................13

Table 4-2. Pins Listed in Alphabetical Order (128-pin LQFP)...........................................................................14

Table 5-1. Pin Descriptions of LPC Bus Interface.............................................................................................15

Table 5-2. Pin Descriptions of External LPC/FWH Flash Interface...................................................................15

Table 5-3. Pin Descriptions of External Serial Flash Interface..........................................................................16

Table 5-4. Pin Descriptions of Keyboard Matrix Scan Interface.......................................................................16

Table 5-5. Pin Descriptions of SM Bus Interface..............................................................................................16

Table 5-6. Pin Descriptions of PS/2 Interface...................................................................................................16

Table 5-7. Pin Descriptions of PWM Interface..................................................................................................17

Table 5-8. Pin Descriptions of Wake Up Control Interface...............................................................................17

Table 5-9. Pin Descriptions of UART Interface.................................................................................................17

Table 5-10. Pin Descriptions of CIR Interface...................................................................................................17

Table 5-11. Pin Descriptions of External GPIO Bus (EGPC) Interface.............................................................18

Table 5-12. Pin Descriptions of Parallel Port Interface.....................................................................................18

Table 5-13. Pin Descriptions of GPIO Interface................................................................................................18

Table 5-14. Pin Descriptions of Hardware Strap...............................................................................................18

Table 5-15. Pin Descriptions of ADC Input Interface........................................................................................19

Table 5-16. Pin Descriptions of DAC Output Interface.....................................................................................19

Table 5-17. Pin Descriptions of Clock...............................................................................................................19

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Contents

Table 5-18. Pin Descriptions of Power/Ground Signals....................................................................................19

Table 5-19. Power States..................................................................................................................................21

Table 5-20. Quick Table of Power Plane for Pins.............................................................................................22

Table 5-21. Pin States of LPC Bus Interface....................................................................................................22

Table 5-22. Pin States of LPC/FWH Flash Interface........................................................................................22

Table 5-23. Pin States of Keyboard Matrix Scan Interface...............................................................................23

Table 5-24. Pin States of SM Bus Interface......................................................................................................23

Table 5-25. Pin States of PS/2 Interface...........................................................................................................23

Table 5-26. Pin States of PWM Interface..........................................................................................................23

Table 5-27. Pin States of Wake Up Control Interface.......................................................................................23

Table 5-28. Pin States of UART Interface.........................................................................................................24

Table 5-29. Pin States of CIR Interface............................................................................................................24

Table 5-30. Pin States of EGPC Interface........................................................................................................24

Table 5-31. Pin States of GPIO Interface..........................................................................................................24

Table 5-32. Pin States of ADC Input Interface..................................................................................................24

Table 5-33. Pin States of DAC Output Interface...............................................................................................24

Table 5-34. Pin States of Clock.........................................................................................................................24

Table 5-35. Reset Sources................................................................................................................................26

Table 5-36. Reset Types and Applied Module..................................................................................................26

Table 5-37. Clock Types...................................................................................................................................27

Table 5-38. Power Saving by EC Clock Operation Mode.................................................................................29

Table 5-39. Module Status in Each Power State/Clock Operation...................................................................30

Table 5-40. Pins with Pull Function...................................................................................................................31

Table 5-41. Pins with Schmitt-Trigger Function................................................................................................31

Table 5-42. Signals with Open-Drain Function.................................................................................................31

Table 6-1. LPC/FWH Response........................................................................................................................36

Table 6-2. Host View Register Map, PNPCFG.................................................................................................38

Table 6-3. Host View Register Map, Logical Devices.......................................................................................38

Table 6-4. Host View Register Map via Index-Data I/O Pair, Standard Plug and Play Configuration Registers39

Table 6-5. Interrupt Request (IRQ) Number Assignment, Logical Device IRQ via SERIRQ............................39

Table 6-6. Logical Device Number (LDN) Assignments...................................................................................40

Table 6-7. Host View Register Map via Index-Data I/O Pair, SWUC Logical Device.......................................46

Table 6-8. Host View Register Map via Index-Data I/O Pair, KBC / Mouse Interface Logical Device..............47

Table 6-9. Host View Register Map via Index-Data I/O Pair, KBC / Keyboard Interface Logical Device.........48

Table 6-10. Host View Register Map via Index-Data I/O Pair, SMFI Interface Logical Device........................50

Table 6-11. Host View Register Map via Index-Data I/O Pair, BRAMLD Logical Device.................................52

Table 6-12. Host View Register Map via Index-Data I/O, PM1 Logical Device................................................54

Table 6-13. Host View Register Map via Index-Data I/O, PM2 Logical Device................................................55

Table 6-14. Mapped Host Memory Address.....................................................................................................61

Table 6-15. EC View Register Map, SMFI........................................................................................................67

Table 6-16. Host View Register Map, SMFI......................................................................................................80

Table 6-17. Host View Register Map, SWUC...................................................................................................86

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Table 6-18. EC View Register Map, SWUC......................................................................................................90

Table 6-19. Host View Register Map, KBC.......................................................................................................97

Table 6-20. EC View Register Map, KBC.........................................................................................................99

Table 6-21. Host View Register Map, PMC....................................................................................................107

Table 6-22. EC View Register Map, PMC.......................................................................................................109

Table 6-23. Host View Register Map, TMKBC................................................................................................115

Table 6-24. EC View Register Map, TMKBC..................................................................................................120

Table 7-1. 8032 Port Usage...........................................................................................................................125

Table 7-2. System Interrupt Table...................................................................................................................127

Table 7-3. Timer 2 Modes of Operation..........................................................................................................133

Table 7-4. Serial Port Signals..........................................................................................................................135

Table 7-5. Selecting the Baud Rate Generator(s)...........................................................................................137

Table 7-6. Internal RAM Map..........................................................................................................................139

Table 7-7. EC View Register Map, INTC........................................................................................................155

Table 7-8. INTC Interrupt Assignments...........................................................................................................162

Table 7-9. EC View Register Map, WUC........................................................................................................165

Table 7-10. WUC Input Assignments..............................................................................................................169

Table 7-11. EC View Register Map, KB Scan.................................................................................................171

Table 7-12. EC View Register Map, GPIO......................................................................................................173

Table 7-13. GPIO Alternate Function..............................................................................................................177

Table 7-14. EC View Register Map, ECPM....................................................................................................182

Table 7-15. EC View Register Map, SMBUS..................................................................................................192

Table 7-16. EC View Register Map, PS/2.......................................................................................................200

Table 7-17. EC View Register Map, DAC.......................................................................................................203

Table 7-18. EC View Register Map, ADC.......................................................................................................209

Table 7-19. Detail Step of ADC Channel Conversion.....................................................................................218

Table 7-20. CR256 Waveform........................................................................................................................224

Table 7-21. CR256 Added Additional Pulse Position......................................................................................225

Table 7-22. EC View Register Map, PWM......................................................................................................228

Table 7-23. EC View Register Map, EC2I.......................................................................................................247

Table 7-24. EC View Register Map, ETWD....................................................................................................252

Table 7-25. EC View Register Map, GCTRL...................................................................................................255

Table 7-26. Modulation Carrier Frequency.....................................................................................................272

Table 7-27. Receiver Demodulation Low Frequency (HCFS = 0)..................................................................274

Table 7-28. Receiver Demodulation High Frequency (HCFS = 1)..................................................................275

Table 7-29. I2EC/D2EC Accessible Targets...................................................................................................281

Table 7-30. EC View Register Map, DBGR....................................................................................................282

Table 9-1. Power Consumption.......................................................................................................................298

Table 10-1. VSTBY Power-on Reset AC Table..............................................................................................299

Table 10-2. Reset AC Table............................................................................................................................300

Table 10-3. Warm Reset AC Table.................................................................................................................300

Table 10-4. Wakeup from Doze Mode AC Table............................................................................................300

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Contents

Table 10-5. Wake Up from Sleep Mode AC Table..........................................................................................301

Table 10-6. Asynchronous External Wakeup/Interrupt Source Edge Detected AC Table..............................301

Table 10-7. LPC and SERIRQ AC Table........................................................................................................301

Table 10-8. SWUC Wake Up AC Table..........................................................................................................302

Table 10-9. LPC/FWH Flash Cycle AC Table.................................................................................................302

Table 10-10. Serial Flash Cycle AC Table......................................................................................................303

Table 10-11. PWM Output AC Table..............................................................................................................303

Table 10-12. PMC SMI#/SCI# AC Table.........................................................................................................304

Table 10-13. PMC IBF/SCI# AC Table...........................................................................................................304

Table 10-14. PS/2 Receive/Transmit AC Table..............................................................................................305

Table 10-15. SMBUS AC Table......................................................................................................................306

Table 10-16. Consumer IR (CIR) AC Table....................................................................................................307

Table 10-17. External GPIO Controller Interface AC Table............................................................................308

Table 11-1. ADC Characteristics.....................................................................................................................309

Table 11-2. DAC Characteristics.....................................................................................................................309

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