无线通信的VLSI技术：第二版

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"VLSI for Wireless Communication 2nd Edition" 本书是关于VLSI（超大规模集成电路）在无线通信中的应用的第二版，由Bosco Leung撰写，他在电气与计算机工程领域有着丰富的教学与研究经验，来自加拿大滑铁卢大学。这本书是之前由Pearson Education, Inc.出版的，现在由Springer Science+Business Media重新发行，具有国际标准书号（ISBN）和数字对象标识符（DOI），确保了其学术性和权威性。 VLSI在无线通信中的应用是现代通信技术的关键组成部分，因为这些微型电路能够集成大量的电子组件，极大地提高了系统的性能和效率。该书涵盖了VLSI设计的核心概念，以及如何将这些设计应用于无线通信系统。这包括但不限于： 1. **VLSI设计基础**：介绍VLSI设计的基本原理，如半导体物理、微电子工艺和电路设计，这些是理解和创建高效集成电路的基础。 2. **无线通信理论**：深入探讨无线通信的基本原理，如信号处理、调制解调技术、信道编码和解码，以及多址接入方法，这些都是VLSI实现无线通信功能时必须考虑的因素。 3. **VLSI实现**：详述如何将无线通信算法转化为硬件实现，包括射频（RF）集成电路、基带处理器、数字信号处理器（DSP）和片上系统（SoC）设计。 4. **低功耗设计**：在无线通信设备中，功耗是至关重要的，书中会讨论各种低功耗设计策略和技术，如动态电压和频率调整、电源管理以及能量效率优化。 5. **射频与微波集成电路**：介绍VLSI在射频和微波频段的设计挑战和解决方案，这对于无线通信的长距离传输至关重要。 6. **无线通信标准**：涵盖多种无线通信标准，如蓝牙、Wi-Fi、LTE、5G等，分析它们对VLSI设计的具体需求和影响。 7. **实验和案例研究**：书中可能包含实际的实验和案例研究，使读者能够理解VLSI在实际无线通信系统中的应用和性能。 8. **最新发展**：由于无线通信领域的快速发展，第二版可能会更新最新的VLSI技术和无线通信趋势，如物联网（IoT）、毫米波通信和大规模MIMO技术。此外，作者提到读者可以通过提供的链接获取额外的书籍材料，这可能是补充阅读、练习题或实验指导，以增强学习体验。对于想要深入理解和设计无线通信系统中VLSI的工程师、学生和研究人员来说，这本书是一份宝贵的资源。

Fig. 1.33 (a) Flat fading, (b) frequency selective fading. . . ........... 49

Fig. 1.34 Irreducible BER as a function of normalized delay

spread for different modulation schemes, frequency

selective fading . . . ................................. 50

Fig. 1.35 OFDM QPSK on multi carriers. ........................ 51

Fig. 1.36 OFDM block diagram implementation ................... 53

Fig. 1.37 Illustration of possible signal reception for the mobile

unit in motion...................................... 54

Fig. 1.38 Power proﬁle of a Doppler shifted channel in the

frequency domain. . ................................. 55

Fig. 1.39 (a) The mobile unit moves at a speed of v with respect

to the Tx antenna, causing time-varying phase changes.

(b) The continuous lines represent the phasors of the two

signals received at time t

(position l) and the dashed lines

represent the phasors of two signals received at time

þDt (position 2). . ................................. 57

Fig. 1.40 BER as a function of SNR, with Doppler effect,

for GMSK modulation . . ............................. 58

Fig. 1.41 Matrix illustrating types of fading experienced by a signal

as a function of (a) baseband signal (symbol) period and

(b) baseband signal bandwidth . ........................ 60

Fig. 2.1 Front end of the receiver enclosed in dotted line . ........... 63

Fig. 2.2 RF receiver using a heterodyne architecture ............... 67

Fig. 2.3 Image rejection problem in the case where FDMA

techniques are used to separate different users . . ........... 69

Fig. 2.4 Diagram showing problem of image and function

of BPF2 .......................................... 71

Fig. 2.5 Frequency spectrum of input, output of the

nonlinear system. . . ................................. 76

Fig. 2.6 The effect of the intermodulation distortion in the frequency

domain, where the frequencies represent the following

signals: o

: desired signal; o

, o

: strong interferers;

,2o

: harmonics of the interferers; o

o

: second

order intermodulation products; 2o

1,2

o

2,1

: third order

intermodulation products ............................. 77

Fig. 2.7 a) The linear gain (a

A) and the nonlinear component

(3/4a

). b) Graphical representation of the input and

output third-order intercept point (IIP

,OIP

).............. 78

Fig. 2.8 Two cascaded nonlinear stages, where a

1,1

and a

1,2

are the

linear gains of stage 1 and 2 and IIP

3,1

and IIP

3,2

denote

the third-order intercept points of stages 1 and 2, z

(t)

denotes the output signal of the ﬁrst stage, and z

(t) denotes

the output signal of the second stage. .................... 79

List of Figures xv

Fig. 2.9 N cascaded nonlinear stages, where a

1,1

...a

1,n

are the linear gains of stage 1...n and IIP

3,1

...IIP

3,n

denote the third order intercept points of stage 1 ... n, z

(t)

denotes the ouput signal of the ﬁrst stage, and z

(t) denotes

the output signal of the n th stage . . . .................... 81

Fig. 2.10 Illustration of the 1-dB compression point . ............... 84

Fig. 2.11 Model used in noise ﬁgure calculations................... 87

Fig. 2.12 Cascade of k gain stages, each with noise . . ............... 88

Fig. 2.13 Receiver block diagram showing the G, NF, IIP

and SNR of the front end ............................. 90

Fig. 2.14 Four users are using their cellular phones at the same time,

where d is the maximum range from user to the base station

(dictated by standards; in our example this equals 400 m);

is the free space distance; d

is the minimum allowable

distance between user 1 and user 2, where user 2 uses

the next channel; and d

is the minimum allowable distance

between user 1 and user 3............................. 92

Fig. 2.15 The signal strength requirements of adjacent channels

in the DECT standard . . . ............................. 93

Fig. 2.16 Block diagram showing signal and interference level

at input and output of receiver front end . . . ............... 93

Fig. 2.17 Frequency spectrum at the output of the receiver

front end.......................................... 94

Fig. 2.18 Two equivalent representations of the front end:

(a) Interferers represented as narrowband noise.

(b) Interferers represented as tones . . .................... 95

Fig. 2.19 Signal strength at the output of the receiver front end . . ...... 98

Fig. 2.20 a) The heterodyne architecture b) The heterodyne

architecture with the corresponding input and output

impedance of the different subcomponents . .............. 100

Fig. 3.1a Generalized LNA topology........................... 108

Fig. 3.1b Lumped parameter representation of ampliﬁer . . .......... 108

Fig. 3.2a LNA using lump ed parameter representation . . . .......... 112

Fig. 3.2b LNA with transformer matching at the input.............. 113

Fig. 3.3a Wideband LNA . . . ................................ 116

Fig. 3.3b The a circuit of core ampliﬁer with loading .............. 117

Fig. 3.3c The f circuit of core ampliﬁer with loading . .............. 118

Fig. 3.4a LNA using inductor at the gate for matching . . . .......... 128

Fig. 3.4b Small-signal equivalent circuit of LNA using inductor

at the gate for matching . ............................ 128

Fig. 3.5a LNA using source degrenerated inductor for matching . ..... 128

Fig. 3.5b Small-signal equivalent circuit of LNA using source

degeneratedinductorformatching......................... 129

Fig. 3.6a Alternative viewpoint of small-signal equivalent circui t ..... 130

xvi List of Figures

Fig. 3.6b Phasor diagram showing I

and V

in phase under

resonance condition. This means input impedance

becomes resistive . . ................................ 130

Fig. 3.6c Phasor diagram showing a situation when V

Under this situation the resonant circuit ampliﬁes V

by a factor Q to obtain V

. Q, the quality factor, becomes

the voltage gain of the matching network . . .............. 131

Fig. 3.7a LNA using inductor at the gate and source degenerated

inductor to achieve matching . . ....................... 133

Fig. 3.7b Small-signal equivalent circuit of LNA using L

, L

for matching. ..................................... 133

Fig. 3.8a Differential implementation of a complete

narrowband LNA . . ................................ 139

Fig. 3.8b Single-ended half of the complete differential

narrowand LNA . . . ................................ 140

Fig. 3.9a Small-signal equivalent circuit of LNA

with noise generators . . . ............................ 141

Fig. 3.9b Representation of Figure 3.9a by two input

noise generators . . . ................................ 141

Fig. 3.10 Representation of Z

using a passive RLC circuit .......... 144

Fig. 3.11a Representation of L

with parasitics using

an equivalent network. . . ............................ 150

Fig. 3.11b Approximation to Figure 3.11a when Q

ind3

1............ 150

Fig. 3.12a Narrowband LNA redrawn, separating the transconductor

from the load ..................................... 151

Fig. 3.12b Small-signal equivalent circuit of Figure 3.12a ............ 152

Fig. 3.13a Small-signal equivalent circuit of Figure 3.12a with

noise generators . . . ................................ 152

Fig. 3.13b Representation of Figure 3.13a by two input

noise generators . . . ................................ 152

Fig. 3.14a Small-signal equivalent circuit of a MOS transistor

including gate resistance due to high-frequency effect . ..... 154

Fig. 3.14b Plot of input admittance of a MOS transistor versus

frequency . . . ..................................... 154

Fig. 3.15a Physical construction of a bond wire inductor . . . .......... 155

Fig. 3.15b Physical construction of a spiral inductor and its complete

equivalent model . . ................................ 155

Fig. 4.1 Mixer modeled as variable gain ampliﬁer . . .............. 164

Fig. 4.2 Plot of the S-function versus the control voltage V

lo.

........ 164

Fig. 4.3 Unbalanced mixer . ................................ 167

Fig. 4.4 Single balanced mixer . . ............................ 167

Fig. 4.5 Alternate single balanced mixer , where LO

and RF ports are swapped............................ 168

Fig. 4.6 Gilbert/quad mixer . ................................ 169

List of Figures xvii

Fig. 4.7 A square wave V

for the Gilbert mixer. The two phases

are shown . . . ..................................... 170

Fig. 4.8 Gilbert mixer output current as a function of time.......... 171

Fig. 4.9 Block diagram of a discrete time LTI system . . . .......... 180

Fig. 4.10 Block diagram of a discrete time, NLTI system . .......... 181

Fig. 4.11 Circuit representation 1 . ............................ 185

Fig. 4.12 A circuit that cannot be represented by circuit

representation 1 . . . ................................ 185

Fig. 4.13 A circuit that can be represented by circuit

representation 1 . . . ................................ 186

Fig. 4.14 Magnitude and phase response of X( jo)................. 187

Fig. 4.15 Circuit representation 2 . ............................ 190

Fig. 4.16 SCP as V-I converter with parasitic capacitance . .......... 192

Fig. 4.17 Block diagram representation of an unbalanced mixer

for noise calculation ................................ 209

Fig. 4.18 Block diagram of the switching part of an unbalanced

mixer . .......................................... 211

Fig. 4.19 Behavior of impulse responses of a LTI system . .......... 212

Fig. 4.20 Behavior of impulse responses of a LPTV system.......... 213

Fig. 4.21 (a), (c) Behavior of h as a function of launch time.

(b), (d) Corresponding g ............................. 214

Fig. 4.22 Impulse response of a mixer operating under

the special V

switching case . . ....................... 218

Fig. 4.23 An equivalent representation of mixer stage 2

in the special V

switching case....................... 219

Fig. 4.24 Mixer stage 2 is represented as a special LPTV system.

The gain part of this special LPTV system is plotted

as a function of launch time . . . ....................... 220

Fig. 4.25 Mixer stage 2 is represented as a special LPTV system.

Frequency response of the LTI system part of this special

LPTV system is shown . . ............................ 224

Fig. 4.26 A complete active mixer. ............................ 228

Fig. 5.1 Unbalanced switching mixer. . . ....................... 232

Fig. 5.2 Double balanced switching mixer . . . ................... 233

Fig. 5.3 Complete distortion model for the unbalanced

switching mixer . . . ................................ 236

Fig. 5.4 Low-frequency distortion model for the unbalanced

switching mixer . . . ................................ 237

Fig. 5.5 Layout of switch M

................................ 241

Fig. 5.6 Conversion gain model for the unbalanced

switching mixer . . . ................................ 243

Fig. 5.7 Noise model for the unbalanced switching mixer .......... 246

Fig. 5.8 Switching mixer and IF ampliﬁer . . . ................... 248

xviii List of Figures

Fig. 5.9 Switching mixer and IF ampliﬁer redrawn with M

replaced by their equivalent impedance ..... 249

Fig. 5.10 Single-ended sampling mixer and sampling operation. . ..... 251

Fig. 5.11 Single-ended sampling mixer and sampling operation:

only envelope of input shown . . ....................... 251

Fig. 5.12 Single-ended sampling mixer and sampling operation:

nonideal effects highlighted . . . ....................... 252

Fig. 5.13 Bottom-plate single-ended sampling mixer . .............. 254

Fig. 5.14 Subsampling operation . . ............................ 255

Fig. 5.15 Conversion gain model for the single-ended

sampling mixer.................................... 257

Fig. 5.16 Distortion model for single-ended sampling mixer

(high frequency, ﬁnite fall time) ....................... 258

Fig. 5.17 Composition of second-order system from ﬁrst-order

systems.......................................... 263

Fig. 5.18 Diagram showing sampling error . . . ................... 272

Fig. 5.19 Bottomplate single-ended sampling mixer with parasitics

capacitance. . ..................................... 274

Fig. 5.20 Receiver front end architecture for Numerical example 5.2. . . 279

Fig. 6.1 FM discriminator, analog ............................ 292

Fig. 6.2 FM discriminator, digital ............................ 293

Fig. 6.3 IF detection, digital ................................ 294

Fig. 6.4 Baseband detection, digital ........................... 294

Fig. 6.5 Baseband detection, hybrid........................... 295

Fig. 6.6 Resolution versus sampling frequency for A/D converters

implemented using different architectures. . .............. 297

Fig. 6.7 Power versus sampling frequency for an 8-bit A/D

converter implemented in different architectures. .......... 298

Fig. 6.8 First order modulator . . . ............................ 300

Fig. 6.9 Model of a ﬁrst order modulator ....................... 301

Fig. 6.10 Second order modulator . ............................ 302

Fig. 6.11 (a) Integrator with forward delay. (b) Integrator

with feedback delay. (c) One type of implementation

of a second-order modulator . . . ....................... 303

Fig. 6.12 N( f ) for ﬁrst and second order modulator . . .............. 304

Fig. 6.13 Third-order modulator . . ............................ 305

Fig. 6.14 Single-ended switched capacitor integrator . .............. 307

Fig. 6.15 N( f ) for ﬁrst and second order modulators with leaky

integrators . . ..................................... 309

Fig. 6.16 Single-ended switched capacitor integrator

with 1-bit DAC.................................... 312

Fig. 6.17 (a) Second-order modulator using only type 1 integrator.

(b) Second-order modulator using only type 1 integrator

and with scaling . . . ................................ 316

List of Figures xix

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