MT6253
GSM/GPRS Baseband Processor Data Sheet
v0.99 Confidential A
MediaTek Confidential © 2009 MediaTek Inc. Page 20 of 601
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
E19 QP
I/O pad for BB analog IQ
F18 QN
I/O pad for BB analog IQ
J31 RFVCO_MT
Monitor pad for RFVCO output
M32 FREF
Monitor pad for DCXO output
K34 XTAL1
Input pad for DCXO crystal
RF Control Circuitry (6 pins)
P34 BPI_BUS5 IO
RF hard-wire control bus bit 5 GPIO82 BPI_BUS5
Output
U29 BPI_BUS4 IO
RF hard-wire control bus bit 4 GPIO81 BPI_BUS4
Output
P32 BPI_BUS3 IO
RF hard-wire control bus bit 3
Output
T30 BPI_BUS2 IO
RF hard-wire control bus bit 2
Output
N33 BPI_BUS1 IO
RF hard-wire control bus bit 1
Output
R31 BPI_BUS0 IO
RF hard-wire control bus bit 0
Output
Digital Audio Interface (5 pins)
AG3
DAICLK IO
DAI interface clock output GPIO15 DAICLK clko5 PU/PD
Output
AF4 DAIPCMOUT IO
DAI PCM data output GPIO16 DAIPCMOUT
PU/PD
Output
AH2
DAIPCMIN IO
DAI PCM data input GPIO17 DAIPCMIN IRDA_PDN
PU/PD
Input
AF6 DAIRST IO
DAI reset signal input GPIO18 DAIRST clko0 IRDA_TX
PU/PD
Input
AJ1 DAISYNC IO
DAI frame synchronization input GPIO19 DAISYNC
XADMUX PU/PD
Input
PWM Interface (1 pins)
Y6 PWM IO
Pulse-width modulated signal GPIO0 PWM CLKSQ_SEL
Alerter PU/PD
Input
JTAG Interface (6 pins)
AK8
JTMS I
JTAG test port mode switch JTMS PU
Input
AM6
JTDI I
JTAG test port data input JTDI PU
Input
AJ9 JTCK I
JTAG test port clock input JTCK PU
Input
AL7 JTRST_B I
JTAG test port reset input JTRST_B
PD
Input
AP6 JRTCK IO
JTAG test port returned clock output JRTCK
Output
AL5 JTDO IO
JTAG test port data output JTDO
Output
Parallel LCD and NAND Interface (21 pins)
AF30
NLD8 IO
LCM Data Port 8 GPIO40 NLD8 EDICK RF_AUXOU PU/PD
Input
AJ31
NLD7 IO
Nand Flash / LCM Data Port 7 GPIO39 NLD7 PU/PD
Input
AG29
NLD6 IO
Nand Flash / LCM Data Port 6 GPIO38 NLD6 PU/PD
Input
AF32
NLD5 IO
Nand Flash / LCM Data Port 5 GPIO37 NLD5 PU/PD
Input
AH30
NLD4 IO
Nand Flash / LCM Data Port 4 GPIO36 NLD4 PU/PD
Input
AE29
NLD3 IO
Nand Flash / LCM Data Port 3 GPIO35 NLD3 PU/PD
Input
AK32
NLD2 IO
Nand Flash / LCM Data Port 2 GPIO34 NLD2 PU/PD
Input
AG31
NLD1 IO
Nand Flash / LCM Data Port 1 GPIO33 NLD1 PU/PD
Input
AE31
NLD0 IO
Nand Flash / LCM Data Port 0 GPIO32 NLD0 PU/PD
Input
AF34
LWRB IO
Parallel display interface Write Strobe GPIO41 LWRB PU/PD
Output
AD30
LPA0 IO
Parallel display interface address output GPIO42 LPA0 BSI_CLK
PU/PD
Output