Xilinx ISE 11.1深入教程

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"ISE_11.1简明教材是一份深度教程，主要针对Xilinx公司的ISE 11.1设计套件。这份教程由Xilinx官方发布，旨在帮助用户进行与Xilinx硬件设备配合的设计开发。文档包含了重要的使用指南、手册、发行说明或规格书，但使用时必须遵循严格的版权规定，未经Xilinx事先书面许可，不得复制、分发、出版、下载、展示、发布或以任何形式传输该文档。" 这篇文档详细介绍了ISE 11.1的深入使用方法，是Xilinx设计工具的关键参考资料。ISE（Integrated Software Environment）是Xilinx提供的一个综合软件环境，用于FPGA（Field-Programmable Gate Array）和 CPLD（Complex Programmable Logic Device）的设计、仿真、综合和编程。在版本11.1中，它可能包含了更优化的功能和改进，以提升设计效率和性能。教程可能涵盖了以下知识点： 1. **设计流程**：从设计输入、逻辑综合、布局布线到配置文件生成的完整流程。 2. **IP核集成**：如何在ISE中使用和管理Xilinx的IP核（ Intellectual Property），这些核提供了预定义的硬件功能模块。 3. **仿真**：使用ISE内置的仿真器进行设计验证，如ISim仿真工具的使用方法。 4. **约束文件**：介绍如何编写和应用xdc（Xilinx Design Constraints）文件来定义设计的时序和物理限制。 5. **硬件编程**：通过JTAG或SPI等接口对FPGA进行配置和编程的步骤。 6. **故障排查**：提供了解决设计问题和错误的指导。 7. **版本更新**：可能包含关于11.1版本相对于前一版本的改进和新增功能的说明。值得注意的是，Xilinx强调他们不对文档内容的准确性承担责任，并且保留随时更改文档的权利，而无需提前通知。用户在使用过程中遇到的任何问题，Xilinx不承担相关责任，这包括技术支持和协助方面。这份ISE 11.1简明教材是学习和掌握Xilinx FPGA/CPLD设计的重要资料，它为开发者提供了详细的指导，帮助他们有效地利用ISE工具实现复杂的硬件设计方案。

16 www.xilinx.com ISE 11 In-Depth Tutorial

UG695 (v 11.2)

Preface:

Libraries Panel

The Libraries tab allows you to manage HDL libraries and their associated HDL source

files. You can create, view, and edit libraries and their associated sources.

Console Panel

The Console provides all standard output from processes run from Project Navigator. It

displays errors, warnings, and information messages. Errors are signified by a red (X) next

to the message, while warnings have a yellow exclamation mark (!).

Errors Panel

Displays only error messages. Other console messages are filtered out.

Warnings Panel

Displays only warning messages. Other console messages are filtered out.

Error Navigation to Source

You can navigate from a synthesis error or warning message in the Console, Errors or

Warnings panel to the location of the error in a source HDL file. To do so, select the error or

warning message, right-click the mouse, and select Go to Source from the right-click

menu.The HDL source file opens and the cursor moves to the line with the error.

Error Navigation to Answer Record

You can navigate from an error or warning message in the Console, Errors or Warnings

panel to relevant Answer Records on the http://www.xilinx.com/support

website. To

navigate to the Answer Record(s), select the error or warning message, right-click the

mouse, and select Go to Answer Record from the right-click menu. The default web

browser opens and displays all Answer Records applicable to this message.

Workspace

The Workspace is where design editors, viewers, and analysis tools will open. These

include ISE Text Editor, Schematic Editor, Timing Constraint Editor, Design Summary &

Report Viewer, RTL and Technology Viewers, and Timing Analyzer.

Other tools such as PlanAhead for I/O planning and floorplanning, ISE Simulator (ISim),

3rd party Text Editors, XPower Analyzer, and iMPACT open in separate windows outside

the main Project Navigator environment when invoked.

Design Summary & Report Viewer

The Design Summary provides a summary of key design data, as well as access to all of the

messages and detailed reports from the synthesis and implementation tools. The summary

lists high-level information about your project, including overview information, a device

utilization summary, performance data gathered from the Place & Route (PAR) report,

constraints information, and summary information from all reports with links to the

ISE 11 In-Depth Tutorial www.xilinx.com 17

UG695 (v 11.2)

Using Project Revision Management Features

individual reports. Messaging features such as message filtering, tagging, and incremental

messaging are also available from this view.

Using Project Revision Management Features

ISE Project File

The ISE® project file (.xise extension) is an XML file that contains all source-relevant data

for the project as follows:

♦ ISE software version information

♦ List of source files contained in the project

♦ Source settings, including design and process properties

The ISE project file does not contain the following:

♦ Process status information

♦ Command history

♦ Constraints data

Note:

A .gise and .ise file also exist, which contain generated data, such as process status. You

should not need to directly interact with these file.

The ISE project file includes the following characteristics, which are compatible with

source control environments:

♦ Contains all of the necessary source settings and input data for the project.

♦ Can be opened in Project Navigator in a read-only state.

♦ Only updated or modified if a source-level change is made to the project.

♦ Can be kept in a directory separate from the generated output directory (working

directory).

Note:

A source–level change is a change to a property or the addition or removal of a source file.

Changes to the contents of a source file or changes to the state of an implementation run are not

considered source-level changes and do not result in an update to the project file.

Making a Copy of a Project

You can create a copy of a project, Project > Copy Project, to experiment with different

source options and implementations. Depending on your needs, the design source files for

the copied project and their location can vary as follows:

♦ Design source files can be left in their existing location, and the copied project

then points to these files.

♦ Design source files, including generated files, can be copied and placed in a

specified directory.

♦ Design source files, excluding generated files, can be copied and placed in a

specified directory.

20 www.xilinx.com ISE 11 In-Depth Tutorial

UG695 (v 11.2)

Chapter 2:

HDL-Based Design

This tutorial assumes that the software is installed in the default location

c:\xilinx\11.1\ISE. If you have installed the software in a different location, substitute your

installation path for c:\xilinx\11.1\ISE in the procedures that follow.

Optional Software Requirements

The following third-party synthesis tools are incorporated into this tutorial, and may be

used in place of the Xilinx Synthesis Tool (XST):

• Synplicity Synplify/Synplify C-2009.3 (or above)

• Mentor Precision Synthesis 2009a.76 (or above)

The following third-party simulation tool is optional for this tutorial, and may be used in

place of the ISE Simulator:

• ModelSim XE/SE/PE 6.4b or newer

VHDL or Verilog?

This tutorial supports both VHDL and Verilog designs, and applies to both designs

simultaneously, noting differences where applicable. You will need to decide which HDL

language you would like to work through for the tutorial, and download the appropriate

files for that language. XST can synthesize a mixed-language design. However, this tutorial

does not go over the mixed language feature.

Installing the Tutorial Project Files

The Stopwatch tutorial projects can be downloaded from

http://www.xilinx.com/support/techsup/tutorials/tutorials1

1.htm. Download either

the VHDL or the Verilog design flow project files.

After you have downloaded the tutorial project files from the web, unzip the tutorial

projects into the c:\xilinx\11.1\ISE\ISEexamples directory, replacing any existing

files in that directory.

When you unzip the tutorial project files into c:\xilinx\11.1\ISE\ISEexamples, the

directory wtut_vhd (for a VHDL design flow) or wtut_ver (for a Verilog design flow) is

created within c:\xilinx\11.1\ISE\ISEexamples, and the tutorial files are copied

into the newly-created directory.

The following table lists the locations of tutorial source files.

Note:

Do not overwrite any files in the solution directories.

Table 2-1:

Tutorial Directories

Directory Description

wtut_vhd Incomplete VHDL Source Files

wtut_ver Incomplete Verilog Source Files

wtut_vhd\wtut_vhd_comple

ted

Completed VHDL Source Files

wtut_ver\wtut_ver_comple

ted

Completed Verilog Source Files

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