Xilinx UG974：最新版宏与基础逻辑介绍

需积分: 5 2 浏览量更新于2024-06-20 2 收藏 6.49MB PDF 举报

本篇文章是来自Xilinx UG974 (v2023.1) 的最新指南，专注于UltraScale架构的Libraries Guide。该文档主要针对AMD Vivado™ Design Suite系列，提供了关于Xilinx原语（如XPM和BUFG）的详细介绍，适用于那些在AMD Adaptive Computing环境中进行高级硬件描述语言（HDL）设计的工程师。文章强调了在2023年版本中，AMD致力于消除产品和相关文档中的非包容性语言，以创建一个更加包容的工作环境。在第一部分，"Introduction"中，概述了该指南的目的，即帮助用户理解和利用UltraScale架构的各种宏（macros）和基本元素（primitives），这些元素构成了设计的核心组件。宏是预定义的代码块，可以简化设计流程，而基本元素则是构成硬件基础的最小可配置单元，如缓冲器（BUFG）用于信号时钟同步，Xilinx Place and Route Macro (XPM)则涉及布局和布线策略的优化。设计元素部分详细列举了在AMD UltraScale架构中支持的功能类别，如逻辑运算、存储器接口、I/O控制等，并对每个功能类别下的元素进行了描述。XPM在此部分特别受到关注，因为它允许设计师自定义逻辑行为，通过参数化和优化算法来提高设计性能和面积效率。 BUFG作为关键的时钟管理单元，它提供了一种简单的方法将系统时钟信号复制到需要的地方，这对于多时钟域设计至关重要。在设计过程中，正确使用BUFG可以确保信号完整性，避免时钟噪声引入和时钟抖动。总结来说，这篇文章是为Xilinx设计者提供的重要参考资料，涵盖了AMD UltraScale架构的最新技术和设计元素，包括XPM和BUFG的使用方法，以及如何在遵循包容性语言原则的同时，实现高效、兼容和优化的硬件设计。对于从事硬件开发的工程师来说，这是深入理解并掌握这些核心工具和技术的关键文档。

XPM_CDC_HANDSHAKE

Parameterized Macro: Bus Synchronizer with Full Handshake

MACRO_GROUP: XPM

MACRO_SUBGROUP: XPM_CDC

Families: UltraScale, UltraScale+

XPM_CDC_HANDSHAKE

src_in[n:0] dest_out[n:0]

dest_clk

src_send

dest_ack

src_clk

dest_req

src_rcv

X15899-031116

Introduction

This macro uses a handshake signaling to transfer an input bus from the source clock domain to

the desnaon clock domain. One example of when this macro should be used is when the data

being transferred is not compable with the XPM_CDC_GRAY macro that uses Gray encoding.

For this macro to funcon correctly, a full handshake—an acknowledgement that the data

transfer was received and a reseng of the handshake signals—must be completed before

another data transfer is iniated.

You can dene the number of register stages used in the synchronizers to transfer the handshake

signals between the clock domains individually. You can also include internal handshake logic to

acknowledge the receipt of data on the desnaon clock domain. When this feature is enabled,

the output (dest_out) must be consumed immediately when the data valid (dest_req) is asserted.

You can also enable a simulaon feature to generate messages to report any potenal misuse of

the macro. These messages will generate errors when the signaling provided to the macro

violates the usage guidance above.

Note: When the XPM_CDC_HANDSHAKE module is used in a design and report_cdc is run, the data bus

that is synchronized in this module is reported as a warning of type CDC-15, Clock Enable Controlled CDC.

This warning is safe to ignore. Starng in 2018.3, this warning has been suppressed by adding a CDC-15

waiver to the Tcl constraint le.

Chapter 2: Xilinx Parameterized Macros

UG974 (v2023.1) May 10, 2023

UltraScale Architecture Libraries Guide 16

Send Feedback

Available Attributes

Attribute Type

Allowed

Values

Default Description

DEST_EXT_HSK DECIMAL 1, 0 1 0- An internal handshake will be implemented in

the macro to acknowledge receipt of data on the

destination clock domain. When using this option,

the valid dest_out output must be consumed

immediately to avoid any data loss.

1- External handshake logic must be implemented

by the user to acknowledge receipt of data on the

destination clock domain.

DEST_SYNC_FF

DECIMAL 2 to 10 4 Number of register stages used to synchronize

signal in the destination clock domain.

INIT_SYNC_FF DECIMAL 0, 1 0 0- Disable behavioral simulation initialization

value(s) on synchronization registers.

1- Enable behavioral simulation initialization

value(s) on synchronization registers.

SIM_ASSERT_CHK DECIMAL 0, 1 0 0- Disable simulation message reporting.

Messages related to potential misuse will not be

reported.

1- Enable simulation message reporting.

Messages related to potential misuse will be

reported.

SRC_SYNC_FF DECIMAL 2 to 10 4 Number of register stages used to synchronize

signal in the source clock domain.

WIDTH DECIMAL 1 to 1024 1 Width of bus that will be synchronized to

destination clock domain.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the enty

declaraon.

Library xpm;

use xpm.vcomponents.all;

-- xpm_cdc_handshake: Bus Synchronizer with Full Handshake

-- Xilinx Parameterized Macro, version 2023.1

xpm_cdc_handshake_inst : xpm_cdc_handshake

generic map (

DEST_EXT_HSK => 1, -- DECIMAL; 0=internal handshake, 1=external handshake

DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10

INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values

SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages

SRC_SYNC_FF => 4, -- DECIMAL; range: 2-10

WIDTH => 1 -- DECIMAL; range: 1-1024

)

port map (

dest_out => dest_out, -- WIDTH-bit output: Input bus (src_in) synchronized to destination clock domain.

-- This output is registered.

dest_req => dest_req, -- 1-bit output: Assertion of this signal indicates that new dest_out data has been

-- received and is ready to be used or captured by the destination logic. When

-- DEST_EXT_HSK = 1, this signal will deassert once the source handshake

-- acknowledges that the destination clock domain has received the transferred

-- data. When DEST_EXT_HSK = 0, this signal asserts for one clock period when

-- dest_out bus is valid. This output is registered.

src_rcv => src_rcv, -- 1-bit output: Acknowledgement from destination logic that src_in has been

Chapter 2: Xilinx Parameterized Macros

UG974 (v2023.1) May 10, 2023

UltraScale Architecture Libraries Guide 19

Send Feedback

-- received. This signal will be deasserted once destination handshake has fully

-- completed, thus completing a full data transfer. This output is registered.

dest_ack => dest_ack, -- 1-bit input: optional; required when DEST_EXT_HSK = 1

dest_clk => dest_clk, -- 1-bit input: Destination clock.

src_clk => src_clk, -- 1-bit input: Source clock.

src_in => src_in, -- WIDTH-bit input: Input bus that will be synchronized to the destination clock

-- domain.

src_send => src_send -- 1-bit input: Assertion of this signal allows the src_in bus to be synchronized

-- to the destination clock domain. This signal should only be asserted when

-- src_rcv is deasserted, indicating that the previous data transfer is complete.

-- This signal should only be deasserted once src_rcv is asserted, acknowledging

-- that the src_in has been received by the destination logic.

);

-- End of xpm_cdc_handshake_inst instantiation

Verilog Instantiation Template

// xpm_cdc_handshake: Bus Synchronizer with Full Handshake

// Xilinx Parameterized Macro, version 2023.1

xpm_cdc_handshake #(

.DEST_EXT_HSK(1), // DECIMAL; 0=internal handshake, 1=external handshake

.DEST_SYNC_FF(4), // DECIMAL; range: 2-10

.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values

.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages

.SRC_SYNC_FF(4), // DECIMAL; range: 2-10

.WIDTH(1) // DECIMAL; range: 1-1024

)

xpm_cdc_handshake_inst (

.dest_out(dest_out), // WIDTH-bit output: Input bus (src_in) synchronized to destination clock domain.

// This output is registered.

.dest_req(dest_req), // 1-bit output: Assertion of this signal indicates that new dest_out data has been

// received and is ready to be used or captured by the destination logic. When

// DEST_EXT_HSK = 1, this signal will deassert once the source handshake

// acknowledges that the destination clock domain has received the transferred data.

// When DEST_EXT_HSK = 0, this signal asserts for one clock period when dest_out bus

// is valid. This output is registered.

.src_rcv(src_rcv), // 1-bit output: Acknowledgement from destination logic that src_in has been

// received. This signal will be deasserted once destination handshake has fully

// completed, thus completing a full data transfer. This output is registered.

.dest_ack(dest_ack), // 1-bit input: optional; required when DEST_EXT_HSK = 1

.dest_clk(dest_clk), // 1-bit input: Destination clock.

.src_clk(src_clk), // 1-bit input: Source clock.

.src_in(src_in), // WIDTH-bit input: Input bus that will be synchronized to the destination clock

// domain.

.src_send(src_send) // 1-bit input: Assertion of this signal allows the src_in bus to be synchronized to

// the destination clock domain. This signal should only be asserted when src_rcv is

// deasserted, indicating that the previous data transfer is complete. This signal

// should only be deasserted once src_rcv is asserted, acknowledging that the src_in

// has been received by the destination logic.

);

// End of xpm_cdc_handshake_inst instantiation

Related Information

XPM CDC Testbench File (xpm-cdc-testbench.zip)

Chapter 2: Xilinx Parameterized Macros

UG974 (v2023.1) May 10, 2023

UltraScale Architecture Libraries Guide 20

Send Feedback

剩余703页未读，继续阅读

Curtain870

粉丝: 428
资源: 3

Xilinx UG974：最新版宏与基础逻辑介绍

vivado-ultrascale-libraries.可用于Xilinx原语查询

Xilinx文档（有助于学习Xilinx）

Xilinx原语详解

xilinx原语的手册

xilinx原语官方文档是哪个

xilinx原语有哪些

xilinx原语全程

xilinx bug 原语 文档

Xilinx FPGA 原语如何配置

Xilinx fpga原语ISERDESE3

最新资源

xilinx bug 原语文档